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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
dc.contributor.author | Bo-Qiao Lin | en |
dc.contributor.author | 林柏僑 | zh_TW |
dc.date.accessioned | 2021-07-11T14:46:25Z | - |
dc.date.available | 2021-10-17 | |
dc.date.copyright | 2016-10-17 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-07-04 | |
dc.identifier.citation | [1] R. K. Ahuja, T. L. Magnanti, and J. B. Orlin, Network Flows: Theory, Algorithms,and Applications. Prentice Hall Englewood Cli s, 1993.
[2] H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, 'Wafer level chip scale package copper pillar probing,' in Proceedings of International Test Conference (ITC), pp. 1-6, October 2014. [3] T. Cormen, C. Leiserson, R. Rivest, and C. Stein, Introduction to Algorithms. MIT press, 2009. [4] J.-W. Fang and Y.-W. Chang, 'Area-I/O flip-chip routing for chip-package co-design,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 518-522, November 2008. [5] ——, 'Area-I/O flip-chip routing for chip-package co-design considering signal skews,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 5, pp. 711-721, May 2010. [6] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, 'An integer-linear-programming-based routing algorithm for flip-chip design,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 606-611, June 2007. [7] ——, 'An integer-linear-programming-based routing algorithm for flip-chip designs,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 98-110, January 2009. [8] J.-W. Fang, Y.-W. C. I.-J. Lin, P.-H. Yuh, and J.-H. Wang, 'A routing algorithm for flip-chip design,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 753-758, November 2005. [9] J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang, 'A network-flow-based RDL routing algorithmz for flip-chip design,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1417-1429, August 2007. [10] J.-W. Fang, M. D. F. Wong, and Y.-W. Chang, 'Flip-chip routing with unified area-I/O pad assignments for package-board co-design,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 336-339, July 2009. [11] Y.-K. Ho, H.-C. Lee, W. Lee, Y.-W. Chang, C.-F. Chang, I.-J. Lin, and C.-F. Shen, 'Obstacle-avoiding free-assignment routing for flip-chip designs,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 2, pp. 224-236, February 2014. [12] Y.-C. Huang, B.-Y. Lin, C.-W. Wu, M. Lee, H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, 'E cient probing schemes for ne-pitch pads of info wafer-level chip-scale package,' in Proceedings of ACM/IEEE Design Automation Conference, 2016. [13] H. W. Kuhn, 'The hungarian method for the assignment problem,' Naval research logistics quarterly,' vol. 2, no. 1-2, pp. 83-97, 1955. [14] H.-C. Lee and Y.-W. Chang, 'A chip-package-board co-design methodology,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 1082-1087, June 2012. [15] H.-C. Lee, Y.-W. Chang, and P.-W. Lee, 'Recent research development in flip-chip routing,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 404-410, November 2010. [16] P.-W. Lee, C.-W. Lin, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, 'An e fficient pre-assignment routing algorithm for flip-chip designs,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 239-244, November 2009. [17] P.-W. Lee, H.-C. Lee, Y.-K. Ho, Y.-W. Chang, C.-F. Chang, I.-J. Lin, and C.-F. Shen, 'Obstacle-avoiding free-assignment routing for flip-chip designs,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 1088-1093, November 2012. [18] C.-W. Lin, P.-W. Lee, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, 'An efficient pre-assignment routing algorithm for flip-chip designs,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 6, pp. 878-889, June 2012. [19] C. C. Liu, S.-M. Chen, F.-W. Kuo, H.-N. Chen, E.-H. Yeh, C.-C. Hsieh, L.-H. Huang, M.-Y. Chiu, J. Yeh, T.-S. Lin, T.-J. Yeh, S.-Y. Hou, J.-P. Hung, J.-C. Lin, C.-P. Jou, C.-T. Wang, S.-P. Jeng, and D. C. H. Yu, 'High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration,' in Proceedings of IEEE International Electron Devices Meeting (IEDM), pp. 14.1.1-14.1.4, December 2012. [20] X. Liu, Y. Zhang, G. K. Yeap, and C. Chu, 'Global routing and track assignment for flip-chip designs,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 90-93, June 2010. [21] L. Luo and M. D. F. Wong, 'Ordered escape routing based on boolean satis fiability,' in Proceedings of IEEE/ACM Asia and South Paci c Design Automation Conference, pp. 244-249, March 2008. [22] D. Staepelaere, J. Jue, T. Dayan, and W. W.-M. Dai, 'Surf: Rubberband routing system for multichip modules,' IEEE Design & Test of Computers, vol. 10, no. 4, pp. 18-26, December 1993. [23] D. J. Staepelaere, Geometric Transformations for a Rubber-Band Sketch. University of California Santa Cruz, 1992. [24] K. J. Supowit, 'Finding a maximum planar subset of a set of nets in a channel,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, no. 1, pp. 93{94, January 1987. [25] T. Szymanski, 'A special case of the maximal common subsequence problem,' Technical Report TR-170, Computer Science Laboratory, Princeton University, Tech. Rep., 1975. [26] J. T. Yan and Z. W. Chen, 'IO connection assignment and RDL routing for flip-chip designs,' in Proceedings of IEEE/ACM Asia and South Paci c Design Automation Conference, pp. 588-593, January 2009. [27] ——, 'RDL pre-assignment routing for flip-chip design,' in Proceedings of the Great Lakes Symposium on VLSI, pp. 401-404, May 2009. [28] ——, 'Pre-assignment RDL routing via extraction of maximal net sequence,' in Proceedings of IEEE International Conference on Computer Design, pp. 65-70, October 2011. [29] T. Yan and M. D. F.Wong, 'Correctly modeling the diagonal capacity in escape routing,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 285-293, February 2012. [30] D. Yu, 'A new integration technology platform: Integrated fan-out wafer-level-packaging for mobile applications,' in Proceedings of the Symposium on VLSI Technology, pp. T46-T47, June 2015. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78217 | - |
dc.description.abstract | 整合扇出型晶圓尺寸封裝 (integrated fan-out wafer-level chip-scale package) 是一個新興的封裝技術,此封裝技術通常會藉由多層重分佈層 (redistribution layer) 來進行多個晶片間的訊號傳輸。目前尚未有發表的論文是針對整合扇出型晶圓尺寸封裝的重分佈層繞線做探討,大部分相關的發表論文著重於考慮覆晶 (flip-chip) 封裝上的重分佈層繞線問題,傳統的覆晶封裝中通常只有單一個晶片,而覆晶封裝上的重分佈層繞線問題可以分為三類,分別是自由配對繞線問題、非自由配對繞線問題與混合型配對繞線問題。由於整合扇出型晶圓尺寸封裝整合了多個晶片,相關的繞線器無法有效地處理此技術的重分佈層繞線問題。為了彌補相關論文缺乏對於多個晶片及多層重分佈層的考慮,我們提出了一個新的整合扇出型晶圓尺寸封裝中的重分佈層繞線問題,此問題考慮到了訊號的完整性、訊號線的分層、重分佈層數量的最小化與總線長的最小化,同時此篇論文提出了第一個針對此問題的演算法。我們提出了一個同心圓模型 (concentric-circle model) 來模擬一個晶片跟其他所有晶片之間的連線,基於此模型,我們將晶片之間的連線分配到適當的重分佈層來避免訊號線過長。除此之外,此模型將晶片間非自由配對連線的幾合資訊整合到了一個網路流模型,此網路流模型可以產生在扇出區域中的繞線雛型。實驗結果顯示我們的演算法的高品質與高效率。 | zh_TW |
dc.description.abstract | The integrated fan-out (InFO) wafer-level chip-scale package (WLCSP) is an emerging packaging technology, which typically consists of multiple redistribution layers (RDLs) for signal redistributions among multiple chips. There is still no published work specifically on the RDL routing for the InFO WLCSP. Published RDL routing works consider different types of RDL routing for flip-chip packages, namely free-assignment, pre-assignment, and unified-assignment routing, for a single chip.
With the integration of multiple chips under the InFO WLCSP, however, previous works cannot achieve high efficiency and effectiveness with simple extensions. To remedy the deficiencies of poor interactions between chips and multiple RDLs, we formulate a new RDL routing problem for the InFO WLCSP and present the first work in the literature to handle the unified-assignment, multi-layer multi-chip RDL routing problem (without RDL vias), considering signal integrity, layer assignment, layer number minimization, and total wirelength minimization. We propose a concentric-circle model which models all the connections among one chip and all other chips. Based on this model, we assign the connections between chips and appropriate layers to avoid long detours. In addition, this model transforms the geometrical information of the pre-assignment connections among chips into a network-flow model to generate a routing prototype in a fan-out region not covered by any chip efficiently and effectively. Experimental results demonstrate the high quality and efficiency of our algorithm. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T14:46:25Z (GMT). No. of bitstreams: 1 ntu-105-R03943099-1.pdf: 2854470 bytes, checksum: 2b229785f23293c59e248aa80493cf31 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | Acknowledgements iii
Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Integrated Fan-Out Wafer-Level Chip-Scale Packages . . . . . . . . . . . 1 1.2 Classication of RDL Routing Problems for Traditional Flip-Chip Pack- ages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Related Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.1 RDL Routing for the Free-Assignment Routing Problem . . . . . 7 1.3.1.1 Network-Flow-Based Methods . . . . . . . . . . . . . . . 7 1.3.1.2 Non-Network-Flow-Based Methods . . . . . . . . . . . . . 10 1.3.2 RDL Routing for the Pre-Assignment Routing Problem . . . . . . 10 1.3.2.1 ILP-Based Methods . . . . . . . . . . . . . . . . . . . . . 10 1.3.2.2 Non-ILP-Based Methods . . . . . . . . . . . . . . . . . . 11 1.3.3 RDL Routing for the Unied-Assignment Routing Problem . . . . 11 1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2. Preliminaries 16 2.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Layout Constraints of Our Problem . . . . . . . . . . . . . . . . . . . . . 19 Chapter 3. An RDL Routing Algorithm 22 3.1 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 Layer Assignment for Pre-Assignment Nets . . . . . . . . . . . . . . . . 23 3.2.1 Concentric-Circle Model . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.2 Construction of the Model for Layer Assignment for Pre-Assignment Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.3 Algorithm Based on the Model . . . . . . . . . . . . . . . . . . . . 27 3.3 Congestion-Aware Escape Routing for All Chips . . . . . . . . . . . . . . 31 3.4 Pad/Layer Assignment for Free-Assignment Nets . . . . . . . . . . . . . 35 3.5 Outward Ring-by-Ring Routing . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 4. Experimental Results 43 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 Experimental Results and Comparisons . . . . . . . . . . . . . . . . . . 44 Chapter 5. Conclusions and Future Work 49 Bibliography 53 Publication List 58 | |
dc.language.iso | zh-TW | |
dc.title | 整合扇出型晶圓尺寸封裝設計之繞線系統 | zh_TW |
dc.title | A Redistribution Layer Routing System for Integrated Fan-Out Wafer-Level Chip-Scale Packages | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 王廷基(Ting-Chi Wang),陳宏明(Hung-Ming Chen),方劭云(Shao-Yun Fang) | |
dc.subject.keyword | 實體設計,整合扇出型晶圓尺寸封裝,重分佈層,重分佈層繞線, | zh_TW |
dc.subject.keyword | Physical Design,Integrated Fan-Out Wafer-Level Chip-Scale Package,Redistribution Layer,RDL Routing, | en |
dc.relation.page | 58 | |
dc.identifier.doi | 10.6342/NTU201600583 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2016-07-05 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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