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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳安宇 | |
dc.contributor.author | Huan-Fu Zeng | en |
dc.contributor.author | 曾煥富 | zh_TW |
dc.date.accessioned | 2021-07-11T14:44:52Z | - |
dc.date.available | 2021-11-03 | |
dc.date.copyright | 2016-11-03 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-01 | |
dc.identifier.citation | [1] L.-T. Wang, C.-W. Wu and X. Wen, VLSI Test Principles and Architectures. Elsevier, 2006.
[2] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits. Kluwer Academic, 2000. [3] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons, 1999. [4] Test and Test Equipment, in International Technology Roadmap for Semiconductors (ITRS-2011), https://www.dropbox.com/sh/r51qrus06k6ehrc/AABnW0tCHso_jKTGwLKyXEJxa/2011Chapters/2011Test.pdf?dl=0 [5] nVidia, http://international.download.nvidia.com/geforce-com/international/pdfs/ GeForce_GTX_980_Whitepaper_FINAL.PDF [6] T. Han, I. Choi and S. Kang, “Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no.8, Aug. 2015. [7] G. Giles, J. Wang, A. Sehgal, K. J. Balakrishnan, and J. Wingfield, “Test Access Mechanism for Multiple Identical Cores,” in IEEE International Test Conference (ITC’08), 2008. [8] M. Sharma, A. Dutta, W.-T. Cheng, B. Benware and M. Kassab, “A Novel Test Access Mechanism for Failure Diagnosis of Multiple Isolated Identical Cores,” in IEEE Internationl Test Conference (ITC 2011), 2011. [9] S. Vangal et al., “An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), 2007. [10] J. Howard et al., 'A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS,' IEEE International Solid-State Circuits Conference (ISSCC), 2010. [11] TILE-Gx 72 Processor, Mellanox, “TILE-Gx Processor Family,” http://www.mellanox.com/page/products_dyn?product_family=238, Feb. 2013. [12] B. Jung and W. P. Burleson, “Efficient VLSI for Lempel–Ziv Compression in Wireless Data Communication Networks,” IEEE Transactions on VLSI Systems, vol. 6, pp. 475–483, Sept. 1998. [13] S. James and S. Thomas, 'Data compression via textual substitution,' Journal of the Association for Computing Machinery, vol. 29, no. 4, October 1982 [14] S. Mitra and K. S. Kim, 'X-Compact: An Efficient Response Compaction Technique, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3, Mar. 2004. [15] Kun-Jin Lin; Cheng-Wen Wu, 'A low-power CAM design for LZ data compression,' IEEE Transactions on Computers, vol.49, no.10, pp.1139-1145, Oct 2000. [16] Lee, C.Y.; Yang, R.-Y., 'High-throughput Data Compressor Designs Using Content Addressable Memory,' IEE Proceedings - Circuits, Devices and Systems, vol.142, no.1, pp. 69-73, Feb 1995. [17] N. Ranganathan and Selwyn Henriques, “High-Speed VLSI Designs for Lempel-Ziv-Based Data Compression,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 40, no. 2, Feb. 1993. [18] Shih-Arn Hwang; Cheng-Wen Wu, 'Unified VLSI systolic array design for LZ data compression,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 4, pp.489-499, Aug. 2001. [19] S. Jones, “100 Mbit/s Adaptive Data Compressor Design Using Selectively Shiftable Content-Addressable Memory,” IEE Proceedings-G, vol. 139, no. 4, pp. 498-502, Aug. 1992. [20] L. Li, K. Chakrabarty and N. A. Touba, “Test Data Compression Using Dictionaries with Selective Entries and Fixed-Length Indices,” ACM Transactions on Design Automation of Electronic Systems, vol. 8, no. 4, pp. 470-490, Oct. 2003. [21] J. Ziv ,and A. Lempel, 'A Universal Algorithm for Sequential Data Compression,' IEEE Transactions on Information Theory, vol. IT-23, no. 3, May 1977. [22] R. Kapur, T. W. Williams, and S. Mitra, “Historical Perspective on Scan Compression”, IEEE Design & Test of Computers, vol. 25, issue 2, pp.115-120, Mar.-Apr. 2008. [23] M. Bellos and D. Nikolos, 'Deterministic Test Vector Compression/Decompression Using an Embedded Processor,' in Proceedings 5th European Dependable Computing Conference (EDCC-5), pp. 318-331, Budapest, Hungary, April 2005. [24] USB 3.1 Specifications, http://www.usb.org/developers/docs/usb_31_052016.zip [25] B. W. Y. Wei, R. Tarver, J.-S. Kim and K. Ng, “A Single Chip Lempel-Ziv Data Compressor,” in IEEE International Symposium on Circuits and Systems (ISCAS’93), pp. 1953-1955, vol.3, May 1993. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78178 | - |
dc.description.abstract | 目前隨著多核心CPU及GPU(圖形處理單元)的普及,且核心數量由多核轉為眾核,測試資料急速的增加。然而由於自動測試機的傳輸頻寬及接腳數目有限,相較於測試資料的增加並未顯著上升,因此造成測試時間的上升,也就是測試成本的提升。為了達到降低測試成本,測試壓縮被廣泛地採用。
測試壓縮可分為測試激勵壓縮(test stimulus compression)及測試響應壓縮(test response compaction)。測試激勵壓縮是指在經由自動測試圖樣產生(ATPG)測試資料後,將測試資料做無損壓縮,並存於自動測試機(ATE)。當進行測試時,由自動測試機讀取測試資料傳輸至待測電路,並經過待測電路上之解壓縮器解壓,再進行測試。測試響應壓縮則是在待測經過測試後,將測試響應做壓縮,傳回自動測試機。在經過測試後,若有錯誤,可由診斷機制判斷錯誤發生之原因。 傳統相同多核心測試響應壓縮,使用有損壓縮方式,以達成高壓縮倍率。然而,這會使診斷進行變得困難。為保留完整測試響應資訊,本論文採用無損的LZSS壓縮演算法。由於無損的特性,可使測試響應壓縮之後,可以保留完整的響應資訊,以利後續的診斷。 在硬體實現方面,我們設計一高速之LZSS解碼器硬體架構,作為晶片內測試激勵壓縮之解壓縮器。同時我們設計一高速、可規模化的LZSS編碼器硬體架構,作為晶片內部測試響應壓縮之壓縮器。本論文提出適用於相同多核心,基於LZSS的無損測試壓縮機制,可以達到高速、可規模化,且可支援診斷機制之測試壓縮系統。 | zh_TW |
dc.description.abstract | As the current multi-core CPU and GPU prevail, and the core number increases from multi-core to many-core, the test data increases rapidly. Due to the limited transmission bandwidth and pin counts of the automatic test equipment (ATE), test time as well as test cost rise. In order to lower test costs, test compression is widely adopted.
Test compression can be divided into test stimulus compression as well as test response compaction. Test stimulus compression refers to the fact that, after the test data is generated using automatic test pattern generation (ATPG), it is compressed and stored in the memory of the ATE. During test, the test data is read out from the ATE memory and decompressed on chip before sending into the design-under-test (DUT). Test response compaction, on the other hand, refers to the fact that after the design under test is tested, the test response data is compressed on-chip and sent back to the ATE. After the test response compaction, we can further analyze the test response to do circuit diagnosis, which refers to finding out the fault that causes the output error. Conventional test response compaction uses lossy compression in order to reach high compressibility. However, it is difficult to diagnose the circuit fault using the compacted test response. In order to better diagnose the circuit, we use lossless compression algorithm, LZSS, to do the test response compaction. Therefore, the full test response information can be utilized to do better circuit diagnosis. This thesis proposes a lossless test compression scheme for identical multicore systems using LZSS compression algorithm. The broadcast-based test stimulus compression does not differ from the single core case much; thus, we focus on the algorithm design for test response compaction. Owing to the lossless compression capability of the LZSS algorithm, test response information is fully sustained after the test response compaction, which can be better utilized in the circuit diagnosis. In the hardware aspect, we first design a high-throughput LZSS-based decoder for test stimulus decompression on-chip. Second, we design a high-speed and scalable LZSS-based encoder for test response compaction on-chip. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T14:44:52Z (GMT). No. of bitstreams: 1 ntu-105-R01943049-1.pdf: 3501763 bytes, checksum: 944f411789c6aac431ab3eaf0ca427f2 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 摘要 i
Abstract iii Table of Contents v List of Figures viii List of Tables xii Chapter 1 Introduction 1 1.1 VLSI Testing and Test Compression 1 1.1.1 VLSI Testing 1 1.1.2 Test Flow and Test Compression 5 1.1.3 Identical Multicore Test Compression System 7 1.2 Motivation and Goal 8 1.2.1 Problem Formulation 8 1.2.2 The Proposed Test Response Compaction Scheme 9 1.2.3 Thesis Goal 10 1.3 Thesis Organization 11 Chapter 2 Review of Test Response Compaction Techniques 12 2.1 Related Works 12 2.1.1 Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores 12 2.1.2 A Novel Test Access Mechanism for Failure Diagnosis of Multiple Isolated Identical Cores 15 2.2 Problems of Related Works 18 2.3 Summary 19 Chapter 3 LZSS-Based Test Compression for Identical Multiple Core Systems 20 3.1 System Description 20 3.2 LZSS Compression Algorithms 21 3.2.1 Introduction to the Algorithm 21 3.2.2 Compression Process 23 3.2.3 Decompression Process 27 3.2.4 LZSS Algorithm Design Parameters 27 3.3 LZSS-Based Test Stimulus Compression 29 3.3.1 Don’t-care Bits Filling 29 3.3.2 Simulation Settings and Results 30 3.4 LZSS-Based Test Response Compaction for Identical Multiple Cores 32 3.4.1 Validation of Suitability 32 3.4.2 Determination of Design Parameters 36 3.5 Summary 38 Chapter 4 Hardware Architectures for Test Stimulus Decompressors and Test Response Compactors 40 4.1 Hardware Architecture for Test Stimulus Decompressor 40 4.1.1 LZSS Decoder Architecture 40 4.1.2 Speed Limitations and Optimal Design 43 4.1.3 Implementation Results 43 4.2 Review of LZSS Encoder Design 46 4.2.1 CAM-based LZSS Encoder 46 4.2.2 Systolic-array-based LZSS Encoder 47 4.2.3 Comparison 48 4.3 Encoder Hardware Architecture 48 4.3.1 Proposed Three-stage CAM-based LZSS Encoder 48 4.3.1 Unfolded Three-stage CAM-based LZSS Encoder 53 4.3.1 Scalability of LZSS Encoder 60 4.3.2 Implementation Results 61 4.4 Summary 62 Chapter 5 Conclusion and Future Works 63 5.1 Main Contributions 63 5.2 Future Directions 64 References 65 | |
dc.language.iso | en | |
dc.title | 適用於相同多核心系統的測試壓縮及診斷機制之LZSS壓縮演算法及硬體架構設計 | zh_TW |
dc.title | LZSS Compression Algorithm and Architecture for Test Compression and Diagnosis of Identical Multicore Systems | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳坤志,李建模 | |
dc.subject.keyword | 測試激勵壓縮,測試響應壓縮,診斷,相同多核心,LZSS,演算法,可規模化,硬體架構, | zh_TW |
dc.subject.keyword | Test stimulus compression,test response compaction,diagnosis,identical multicore,LZSS,algorithm,scalable,hardware architecture, | en |
dc.relation.page | 68 | |
dc.identifier.doi | 10.6342/NTU201601397 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2016-08-02 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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