Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78178
Title: | 適用於相同多核心系統的測試壓縮及診斷機制之LZSS壓縮演算法及硬體架構設計 LZSS Compression Algorithm and Architecture for Test Compression and Diagnosis of Identical Multicore Systems |
Authors: | Huan-Fu Zeng 曾煥富 |
Advisor: | 吳安宇 |
Keyword: | 測試激勵壓縮,測試響應壓縮,診斷,相同多核心,LZSS,演算法,可規模化,硬體架構, Test stimulus compression,test response compaction,diagnosis,identical multicore,LZSS,algorithm,scalable,hardware architecture, |
Publication Year : | 2016 |
Degree: | 碩士 |
Abstract: | 目前隨著多核心CPU及GPU(圖形處理單元)的普及,且核心數量由多核轉為眾核,測試資料急速的增加。然而由於自動測試機的傳輸頻寬及接腳數目有限,相較於測試資料的增加並未顯著上升,因此造成測試時間的上升,也就是測試成本的提升。為了達到降低測試成本,測試壓縮被廣泛地採用。
測試壓縮可分為測試激勵壓縮(test stimulus compression)及測試響應壓縮(test response compaction)。測試激勵壓縮是指在經由自動測試圖樣產生(ATPG)測試資料後,將測試資料做無損壓縮,並存於自動測試機(ATE)。當進行測試時,由自動測試機讀取測試資料傳輸至待測電路,並經過待測電路上之解壓縮器解壓,再進行測試。測試響應壓縮則是在待測經過測試後,將測試響應做壓縮,傳回自動測試機。在經過測試後,若有錯誤,可由診斷機制判斷錯誤發生之原因。 傳統相同多核心測試響應壓縮,使用有損壓縮方式,以達成高壓縮倍率。然而,這會使診斷進行變得困難。為保留完整測試響應資訊,本論文採用無損的LZSS壓縮演算法。由於無損的特性,可使測試響應壓縮之後,可以保留完整的響應資訊,以利後續的診斷。 在硬體實現方面,我們設計一高速之LZSS解碼器硬體架構,作為晶片內測試激勵壓縮之解壓縮器。同時我們設計一高速、可規模化的LZSS編碼器硬體架構,作為晶片內部測試響應壓縮之壓縮器。本論文提出適用於相同多核心,基於LZSS的無損測試壓縮機制,可以達到高速、可規模化,且可支援診斷機制之測試壓縮系統。 As the current multi-core CPU and GPU prevail, and the core number increases from multi-core to many-core, the test data increases rapidly. Due to the limited transmission bandwidth and pin counts of the automatic test equipment (ATE), test time as well as test cost rise. In order to lower test costs, test compression is widely adopted. Test compression can be divided into test stimulus compression as well as test response compaction. Test stimulus compression refers to the fact that, after the test data is generated using automatic test pattern generation (ATPG), it is compressed and stored in the memory of the ATE. During test, the test data is read out from the ATE memory and decompressed on chip before sending into the design-under-test (DUT). Test response compaction, on the other hand, refers to the fact that after the design under test is tested, the test response data is compressed on-chip and sent back to the ATE. After the test response compaction, we can further analyze the test response to do circuit diagnosis, which refers to finding out the fault that causes the output error. Conventional test response compaction uses lossy compression in order to reach high compressibility. However, it is difficult to diagnose the circuit fault using the compacted test response. In order to better diagnose the circuit, we use lossless compression algorithm, LZSS, to do the test response compaction. Therefore, the full test response information can be utilized to do better circuit diagnosis. This thesis proposes a lossless test compression scheme for identical multicore systems using LZSS compression algorithm. The broadcast-based test stimulus compression does not differ from the single core case much; thus, we focus on the algorithm design for test response compaction. Owing to the lossless compression capability of the LZSS algorithm, test response information is fully sustained after the test response compaction, which can be better utilized in the circuit diagnosis. In the hardware aspect, we first design a high-throughput LZSS-based decoder for test stimulus decompression on-chip. Second, we design a high-speed and scalable LZSS-based encoder for test response compaction on-chip. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78178 |
DOI: | 10.6342/NTU201601397 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
---|---|---|---|
ntu-105-R01943049-1.pdf Restricted Access | 3.42 MB | Adobe PDF |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.