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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳奕君(I-Chun Cheng) | |
dc.contributor.author | Yi-An Shih | en |
dc.contributor.author | 施易安 | zh_TW |
dc.date.accessioned | 2021-07-11T14:41:20Z | - |
dc.date.available | 2021-10-26 | |
dc.date.copyright | 2016-10-26 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2016-08-21 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78071 | - |
dc.description.abstract | 本實驗著重研究以低溫製程方式製作N型下閘極SnOx薄膜電晶體,其特點在於先以濺鍍方式製作出P型氧化亞錫薄膜電晶體,接著再以電漿輔助化學氣相沉積法於電晶體背通道上沉積SiOx薄膜作為覆蓋層,搭配低溫後退火處理,使P型通道轉變成N型通道,實現N型錫氧化物薄膜電晶體。研究中探討SiOx背通道覆蓋層製程參數(如:電漿功率、基板溫度、覆蓋層厚度等)對N型SnOx電晶體特性的影響,並發現覆蓋層中的羥基含量為造成SnOx主動層電性上差異的主要原因。
本研究所開發的製程擁有兩種優點:一為製程最高溫僅為225℃,有利於與可撓性塑膠基板結合;二為以覆蓋層作為後處理方式,搭配微影製程定義覆蓋區域,可在選定之區域形成N型通道,其餘部分則維持P型特性當應用於互補式邏輯閘(CMOS)元件製程上可以單一製程步驟同時沉積P型與N型主動層。綜合以上兩種優點,將有助於軟性互補式氧化物邏輯閘技術的開發。 | zh_TW |
dc.description.abstract | In this research, we have demonstrated inverted-staggered bottom-gate N-type SnOx thin-film transistors (TFTs) via a low-temperature process. It is achieved by introducing a plasma-enhanced chemical vapor deposited SiOx capping layer on the back channel of P-type tin monoxide (SnO) TFTs. The P-type SnO channel turned into N-type after a low-temperature post annealing process was applied. The influence of process parameters of the SiOx capping layer, including the deposition power, substrate temperature, and thickness of the capping layer, on the electrical performance of SnOx TFTs was investigated. We found that the electrical performance of SnOx TFTs was highly dependent on the amount of hydroxyl groups (-OH groups) in the SiOx capping layer.
The developed process possesses two advantages. First, the maximum process temperature is 225℃, which is compatible with flexible polymer substrates. Second, conversion from P-type to N-type can be achieved at selective regions by using a patterned capping layer via a lithography technology. In other words, the P and N active channels can be deposited using a single step. This process is beneficial to the development of flexible oxide-semiconductor-based complementary-metal-oxide-semiconductor (CMOS) circuit technology. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T14:41:20Z (GMT). No. of bitstreams: 1 ntu-104-R03941098-1.pdf: 4355962 bytes, checksum: ad89bfa059188cb29969c3d3916ee004 (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 致謝 I
摘要 II Abstract III 圖目錄 VI 表目錄 IX 第一章 緒論 1 1.1 薄膜電晶體發展背景 1 1.2 研究動機 2 1.3 論文架構 3 第二章 理論與文獻回顧 4 2.1 薄膜電晶體簡介 4 2.2 薄膜電晶體工作原理 5 2.3 薄膜電晶體之特徵參數 6 2.4 氧化亞錫的能階 10 2.5 錫-氧系統相圖 12 2.6 錫氧化物N型薄膜電晶體的發展 13 第三章 研究方法 25 3.1 薄膜沉積儀器 25 3.1.1 原子層沉積系統 25 3.1.2 射頻磁控濺鍍系統 27 3.1.3 電子束蒸鍍系統 29 3.1.4 電漿輔助化學氣相沉積系統 29 3.2 微影製程 30 3.3 蝕刻製程 33 3.4 氧化亞錫薄膜電晶體製備流程 34 3.5 氧化亞錫薄膜電晶體後處理製備流程 38 3.6 量測分析 39 3.6.1 傅立葉轉紅外線光譜儀 39 3.6.2 X光繞射儀 40 3.6.3 薄膜電晶體特性量測方法 41 3.6.4 X光光電子能譜儀 42 第四章 結果與討論 43 4.1 X射線光電子能譜儀分析 (XPS) 43 4.2 氧化亞錫(SnO)與SnOx薄膜結晶相分析 45 4.3 SiOx覆蓋層之傅立葉轉換紅外光譜分析 46 4.4 氧化亞錫薄膜電晶體元件特性分析 49 4.5 SnOx薄膜電晶體元件特性分析 51 4.5.1 SiOx覆蓋層厚度對N型SnOx薄膜電晶體電性影響 51 4.5.2 後退火時間對N型SnOx薄膜電晶體之電性影響 54 4.5.3 SiOx覆蓋層沉積溫度對N型SnOx薄膜電晶體之電性影響 55 4.5.4 SiOx製程電漿功率對N型SnOx薄膜電晶體之電性影響 58 4.6 綜合討論 61 第五章 結論與未來展望 66 5.1 結論 66 5.2 未來展望 67 參考文獻 68 | |
dc.language.iso | zh-TW | |
dc.title | 以背覆蓋層氧化效應製備之低溫N型SnOx薄膜電晶體之研究 | zh_TW |
dc.title | N-type Operation of Low-Temperature SnOx Thin-Film Transistors Induced by Capping Layer Assisted Back-Channel Oxidation | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳建彰(Jian-Zhang Chen),吳志毅(Chi-I Wu),吳育任(Yuh-Renn Wu) | |
dc.subject.keyword | N型氧化物薄膜電晶體,錫氧化物薄膜電晶體,SnOx, | zh_TW |
dc.subject.keyword | N-type oxide thin-film transistors,tin oxide thin-film transistors,SnOx, | en |
dc.relation.page | 73 | |
dc.identifier.doi | 10.6342/NTU201603358 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2016-08-22 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
顯示於系所單位: | 光電工程學研究所 |
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