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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃天偉 | |
dc.contributor.author | Teng-Yuan Chang | en |
dc.contributor.author | 張騰遠 | zh_TW |
dc.date.accessioned | 2021-07-11T14:37:40Z | - |
dc.date.available | 2022-08-30 | |
dc.date.copyright | 2017-08-30 | |
dc.date.issued | 2017 | |
dc.date.submitted | 2017-08-07 | |
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Richardson, 'GaAs PHEMT Power Amplifier MMIC with Integrated ESD Protection for Full SMD 38-GHz Ra-dio Chipset,' 2007 IEEE Compound Semiconductor Integrated Circuits Symposium, Portland, OR, 2007, pp. 1-4. [7] P. C. Huang, Z. M. Tsai, K. Y. Lin and H. Wang, 'A 17–35 GHz Broadband, High Efficiency PHEMT Power Amplifier Using Synthesized Transformer Matching Technique,' in IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 1, pp. 112-119, Jan. 2012. [8] D. P. Nguyen, T. Pham, B. L. Pham and A. V. Pham, 'A High Efficiency High Power Density Harmonic-Tuned Ka Band Stacked-FET GaAs Power Amplifi-er,' 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Austin, TX, 2016, pp. 1-4. [9] D. P. Nguyen and A. V. Pham, 'An Ultra Compact Watt-Level Ka-Band Stacked-FET Power Amplifier,' in IEEE Microwave and Wireless Components Let-ters, vol. 26, no. 7, pp. 516-518, July 2016. [10] K. Yamauchi, K. Mori, M. Nakayama, Y. Mitsui and T. Takagi, 'A microwave min-iaturized linearizer using a parallel diode with a bias feed resistance,' in IEEE Transactions on Microwave Theory and Techniques, vol. 45, no. 12, pp. 2431-2435, Dec 1997. [11] Jeng-Han Tsai, Hong-Yeh Chang, Pei-Si Wu, Yi-Lin Lee, Tian-Wei Huang and Huei Wang, 'Design and analysis of a 44-GHz MMIC low-loss built-in linearizer for high-linearity medium power amplifiers,' in IEEE Transactions on Microwave The-ory and Techniques, vol. 54, no. 6, pp. 2487-2496, June 2006. [12] J. H. Tsai and T. W. Huang, 'A 38–46 GHz MMIC Doherty Power Amplifier Using Post-Distortion Linearization,' in IEEE Microwave and Wireless Components Let-ters, vol. 17, no. 5, pp. 388-390, May 2007. [13] J. H. Tsai, C. H. Wu, H. Y. Yang and T. W. Huang, 'A 60 GHz CMOS Power Am-plifier With Built-in Pre-Distortion Linearizer,' in IEEE Microwave and Wireless Components Letters, vol. 21, no. 12, pp. 676-678, Dec. 2011. [14] N. C. Kuo, J. L. Kuo and H. Wang, 'Novel MMIC Power Amplifier Linearization Utilizing Input Reflected Nonlinearity,' in IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 3, pp. 542-554, March 2012. [15] K. Y. Kao, Y. C. Hsu, K. W. Chen and K. Y. Lin, 'Phase-Delay Cold-FET Pre-Distortion Linearizer for Millimeter-Wave CMOS Power Amplifiers,' in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 12, pp. 4505-4519, Dec. 2013. [16] T. Y. Huang, Y. H. Lin and H. Wang, 'A K-Band adaptive-bias power amplifier with enhanced linearizer using 0.18-µm CMOS process,' 2015 IEEE MTT-S Internation-al Microwave Symposium, Phoenix, AZ, 2015, pp. 1-3. [17] D. P. Nguyen, T. Nguyen and A. V. Pham, 'Development of a highly linear Ka-band power amplifier using second harmonic injection linearization,' 2016 46th European Microwave Conference (EuMC), London, 2016, pp. 835-838. [18] YunSeong Eo and KwangDu Lee, 'A fully integrated 24-dBm CMOS power ampli-fier for 802.11a WLAN applications,' in IEEE Microwave and Wireless Compo-nents Letters, vol. 14, no. 11, pp. 504-506, Nov. 2004. [19] H. Solar, R. Berenguer, I. Adin, U. Alvarado and I. Cendoya, 'A Fully Integrated 26.5 dBm CMOS Power Amplifier for IEEE 802.11a WLAN Standard with on-chip 'power inductors',' 2006 IEEE MTT-S International Microwave Symposium Digest, San Francisco, CA, 2006, pp. 1875-1878. [20] J. H. Tsai and H. W. Ou-Yang, 'A 5–5.8 GHz fully-integrated CMOS PA for WLAN applications,' 2014 IEEE Radio and Wireless Symposium (RWS), Newport Beach, CA, 2014, pp. 130-132. [21] K. C. Lin, H. K. Chiou, P. C. Wu, C. L. Ko, H. H. Tsai and Y. Z. Juang, 'A 28 dBm Pout 5-GHz CMOS power amplifier using integrated passive device power combin-ing transformer,' 2013 Asia-Pacific Microwave Conference Proceedings (APMC), Seoul, 2013, pp. [22] K. C. Lin, H. K. Chiou, P. C. Wu, H. H. Tsai and Y. Z. Juang, '5-GHz SiGe linear-ity power amplifier using integrated feedforward architecture for WLAN applica-tions,' 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 1508-1511. [23] C. Tzschoppe, R. Wolf, D. Fritsche, A. Richter and F. Ellinger, 'A fully integrated Doherty-amplifier for 5.6 GHz WLAN applications,' 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), Marseille, 2014, pp. 72-75. [24] Y. C. Lee, H. Y. Li and J. S. Fu, 'SiGe BiCMOS power amplifier with a switchable output matching network for efficiency enhancement,' 2015 IEEE Radio and Wire-less Symposium (RWS), San Diego, CA, 2015, pp. 62-64. [25] M. L. Lee, C. Y. Liou, W. T. Tsai, C. Y. Lou, H. L. Hsu and S. G. Mao, 'Fully Monolithic BiCMOS Reconfigurable Power Amplifier for Multi-Mode and Mul-ti-Band Applications,' in IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 2, pp. 614-624, Feb. 2015. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77931 | - |
dc.description.abstract | 隨著第五代行動通訊(5G)相關研究之發展,未來的無線系統預期將往毫米波頻段演進,以提供更寬的頻寬以及更高傳輸速率的傳輸。
本論文主要分成三部分:第一部分為發射機前端電路之功率放大器相關研究。 此部分展示了應用於38GHz之增強型 (E-mode) 0.15微米砷化鎵 (GaAs)製程功率放大器。此功率放大器採用四路直接功率結合架構。此提出之功率放大器於38到40 GHz操作頻率下達到了24.7 dBm '±' 0.5 dB 之1 dB壓縮點輸出功率、25.2 dBm '±' 0.3 dB之飽和輸出功率、19.5 '±' 2.7 % 之最大功率附加效率,以及提供19.1 dB之小訊號增益。 第二部分展示了應用於38GHz之空乏型 (D-mode) 0.15微米砷化鎵 (GaAs) 製程具備線性器之功率放大器。此功率放大器運用一並聯二極體線性器來降低三階交互調變信號,以提高線性度,於37到39 GHz操作頻率下達到23.2 dBm '±' 0.5 dB之1dB壓縮點輸出功率、23.6 dBm '±' 0.3 dB之飽和輸出功率、25 '±' 1.8 % 之最大功率附加效率、22.3 dB之小訊號增益,以及在線性器開啟狀況下可提供19.4 dBm之線性輸出功率同時在三階交互調變失真可降低至-55.9 dBc。 第三部分之功率放大器製作於180nm SiGe BiCMOS製程。此功率放大器在5 GHz提供9.2 dB之小信號增益、25.9 dBm 之1 dB壓縮點輸出功率、26.6 dBm 之飽和輸出功率以及14.3 %之最大功率附加效率。 | zh_TW |
dc.description.abstract | With the development of 5G mobile communication, the wireless communication system is expected to advance to millimeter wave (mm-wave) for broader bandwidth and high data rate transmission.
This thesis is divided into three parts. The first part is the research of power amplifier which is the front end circuit of transmitter. The proposed PA operated at 38 GHz is fabricated in 0.15-µm enhancement mode (E-mode) GaAs PHEMT process. The proposed power amplifier utilizing 4-way direct-combining structure achieves OP1dB of 24.7 dBm '±' 0.5 dB, Psat of 25.2 dBm '±' 0.3 dB with 22.2 '±' 1.5 % PAEmax in the frequency range of 38 to 40 GHz and provides small signal gain of 19.1 dB. The second part shows the power amplifier operated at 38 GHz with diode linearizer which is fabricated in 0.15-µm depletion mode (D-mode) GaAs PHEMT process. This proposed PA utilizes a parallel diode to reduce third-order intermodulation for the improvement of linearity. The proposed power amplifier achieves OP1dB of 23.2 dBm '±' 0.5 dB, Psat of 23.6 dBm '±' 0.3 dB with 25 '±' 1.8 % PAEmax in the frequency range of 37 to 39 GHz and provides small signal gain of 22.3 dB. When linearizer turns on, it achieves linear output power of 19.4 dBm and reduces IMD3 to -55.9 dBc simultaneously. The power amplifier of the third part is fabricated in 0.18-um SiGe BiCMOS process. The proposed PA provides small signal gain of 9.2 dB. It achieves OP1dB of 25.9 dBm and Psat of 26.6 dBm with PAEmax of 14.3 % at 5 GHz. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T14:37:40Z (GMT). No. of bitstreams: 1 ntu-106-R04942006-1.pdf: 13698934 bytes, checksum: 5128a359493f19453675d497cf3bdcc6 (MD5) Previous issue date: 2017 | en |
dc.description.tableofcontents | CONTENTS
中文摘要 i ABSTRACT ii CONTENTS iii LIST OF FIGURES v LIST OF TABLES xi Chapter 1 Introduction 12 1.1 Background and Motivation 12 1.2 Thesis Organization 13 Chapter 2 Design of a 38-GHz Power Amplifier in 0.15-µm E-mode GaAs PHEMT process 14 2.1 Introduction 14 2.2 Circuit Design 15 2.2.1 Device Size and Bias Point Selection 16 2.2.2 Driver Stage Deign 23 2.2.3 Circuit Simulation 25 2.3 Experimental Results 31 2.3.1 Measurement Results 31 2.3.2 Discussion 36 2.4 Summary 41 Chapter 3 Design of a 38-GHz Power Amplifier with Diode Linearizer in 0.15-µm D-mode GaAs PHEMT process 43 3.1 Introduction 43 3.2 Circuit Design 44 3.2.1 Device Size and Bias Point Selection 44 3.2.2 Driver Stage Design 51 3.2.3 Diode Linearizer 54 3.2.4 Circuit Simulation 58 3.3 Experiment Results 64 3.3.1 Measurement Results 64 3.3.2 Discussion 71 3.4 Summary 72 Chapter 4 Design of a 5-GHz Power Amplifier in 0.18-µm SiGe BiCMOS process 74 4.1 Introduction 74 4.2 Circuit Design 75 4.2.1 Device Size and Bias Point Selection 75 4.2.2 Matching Networks 80 4.2.3 Circuit Simulation 82 4.3 Experimental Results 85 4.3.1 Measurement Results 85 4.4 Summary 87 Chapter 5 Conclusions 89 References 90 | |
dc.language.iso | en | |
dc.title | 應用於5G行動通訊之砷化鎵功率放大器與應用於WLAN之功率放大器研究 | zh_TW |
dc.title | Research of GaAs Power Amplifiers for 5G mobile communication and Power Amplifier for WLAN Applications | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蔡政翰,蔡作敏 | |
dc.subject.keyword | 增強型與空乏型砷化鎵假型高速電子場效電晶體,線性器,5G無線系統,功率放大器, | zh_TW |
dc.subject.keyword | E-mode and D-mode GaAs PHEMT,linearizer,5G wireless systems,power amplifier, | en |
dc.relation.page | 93 | |
dc.identifier.doi | 10.6342/NTU201702651 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2017-08-07 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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