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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
dc.contributor.author | Yen-Yi Wu | en |
dc.contributor.author | 吳彥儀 | zh_TW |
dc.date.accessioned | 2021-07-11T14:37:12Z | - |
dc.date.available | 2022-08-31 | |
dc.date.copyright | 2017-08-31 | |
dc.date.issued | 2017 | |
dc.date.submitted | 2017-08-14 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77909 | - |
dc.description.abstract | 多重排高元件設計在諸如FinFET 等的先進技術中盛行,隨著製
程技術的縮小,複雜的最小植入面積限制在現代電路設計中產生了 新的挑戰,這也對多重排高標準元件擺置帶來了額外的困難。現有 的單排高度標準元件並考慮最小植入面積的細部擺置在多重排高設 計會有兩方面的不足:(1)傳統上,使用加入相同臨界電壓的填充 物解決違反最小植入面積的標準元件,此舉可能對整個晶片布局造 成龐大的面積和電線長度損失。以及(2)移動多重排高標準元件可 能會導致嚴重的違反行間最小植入面積限制。因此,在這篇論文 裡,我們提出了文獻上第一個考慮行內和行間的最小植入面積限制 的多重排高細部擺置問題。我們首先將違反最小植入面積且相同臨 界電壓的多重排高元件群聚來達成行內最小植入面積限制。接著我們重新擺置群聚內部的多重排高元件位置以獲得更好的單元群聚排 列。使用基於網絡流為基礎的方法,將剩餘違反行內最小植入面積 的多重排高元件置於預期的填充物插入位置,如此可以解決違反行 內最小植入面積的多重排高元件,同時減少填充物所帶來的面積負 荷。在進行多重排高群聚細部擺置後,我們最後透過最小移動距離 推移違反行間最小植入面積的多重排高群聚。與填充插入法和貪婪 群聚演算法相比,實驗結果顯示,我們提出的演算法在合理的運行 時間內以最小的線長和面積負荷來解決所有行內與行間的最小植入 面積限制違規。 | zh_TW |
dc.description.abstract | Mixed-cell-height designs have prevailed in advanced technology such as FinFET-based circuits. Along with the device scaling, complex minimum implant area (MIA) constraints arise as an emerging challenge in modern circuit designs, which incur additional difficulties for mixed-cell-height placement. Existing MIA-aware detailed placement with single-row-height standard cells are insufficient for mixed-cell-height designs in two aspects: (1) filler insertion, typically used to resolve MIA violations, might incur unaffordable area and wirelength penalty, and (2) moving mixed-height cells could incur severe inter-row MIA violations. This thesis presents the first work to address the mixed-cell-height detailed placement problem considering both intra- and inter-row MIA constraints. We first fix intra-row violations by clustering violating mixed-height cells of the same VT. We then perturb each cluster to obtain a better cell permutation. With a network-flow-based formulation, remaining violating cells are placed in the intended-filler-insertion positions, fixing cell violations while reducing area overhead. After performing mixed-cell-height detailed placement, we finally fix inter-row violations by shifting violating cells in minimum displacement. Compared with the filler insertion method and the greedy cluster approach, experimental results demonstrate that our proposed algorithm resolves all MIA violations with least HPWL and area penalty in reasonable running time. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T14:37:12Z (GMT). No. of bitstreams: 1 ntu-106-R04943098-1.pdf: 13455709 bytes, checksum: bad67e19e837906bbbef518aa9ca2af5 (MD5) Previous issue date: 2017 | en |
dc.description.tableofcontents | Abstract (Chinese) iii
Abstract v List of Tables ix List of Figures x Chapter 1. Introduction 1 1.1 Advanced Standard Cell Designs 1 1.1.1 Mixed-Cell-Height Cell Structure 2 1.1.2 Multiple Threshold Voltage Transistor Structure 4 1.2 MIA-Constrained Mixed-Cell-Height Placement Problem 6 1.3 Related Work 8 1.3.1 Mixed-Cell-Height Placement 8 1.3.2 MIA-Aware Placement 10 1.4 Motivation 12 1.5 Our Contributions 13 1.6 Thesis Organization 14 Chapter 2. Preliminaries 17 2.1 Notations 17 2.2 Problem Formulation 18 Chapter 3. MIA-Aware Mixed-Cell-Height Detailed Placement 19 3.1 Algorithm Overview 19 3.2 The Mixed-Cell-Height Clustering Stage 20 3.2.1 Window-Based Clustering 20 3.2.2 DP-Based Cluster Reshaping 22 3.2.3 Algorithm-DLX-Based Cluster Reshaping 25 3.3 The Cluster-Based Mixed-Cell-Height Detailed Placement Stage 30 3.3.1 Cluster-Based Global Moving 30 3.3.2 Cluster-Based Filler Minimization 33 3.3.3 Cluster-Based Matching 36 3.3.4 Cluster-Based Swapping 36 3.4 The Inter-Row MIA Violation Refinement Stage 36 3.4.1 Inter-Row MIA Refinement 38 3.4.2 MIA-Aware Compaction 40 Chapter 4. Experimental Results 43 4.1 Experimental Setup 43 4.2 Comparison and Analysis 44 Chapter 5. Conclusions and Future Work 49 Bibliography 54 Publication List 58 | |
dc.language.iso | zh-TW | |
dc.title | 考慮最小植入層面積之多重排高標準元件細部擺置 | zh_TW |
dc.title | Mixed-Cell-Height Detailed Placement Considering Complex
Minimum-Implant-Area Constraints | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃婷婷(Ting-Ting Hwang),江蕙如(Hui-Ru Jiang),方劭云(Shao-Yun Fang) | |
dc.subject.keyword | 實體設計,電路擺置,漏電流,晶片效能,植入層面積, | zh_TW |
dc.subject.keyword | Physical Design,Placement,Leakage Power,Timing Optimization,Implant Area, | en |
dc.relation.page | 72 | |
dc.identifier.doi | 10.6342/NTU201702856 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2017-08-14 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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