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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77777完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭大維(Tei-Wei Kuo) | |
| dc.contributor.author | Chin-Chiang Pan | en |
| dc.contributor.author | 潘勤强 | zh_TW |
| dc.date.accessioned | 2021-07-11T14:34:39Z | - |
| dc.date.available | 2023-08-14 | |
| dc.date.copyright | 2018-08-14 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-07-23 | |
| dc.identifier.citation | [1] Toshiba MOS Digital Integrated Circuit Silicon Gate CMOS, Tokyo, Japan 2012.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77777 | - |
| dc.description.abstract | 過去十年來，非揮發性記憶體 (如，快閃記憶體及相變化記憶體) 的應用遍佈生活中各項領域，從消費性電子、個人電腦、企業儲存乃 至物聯網與汽車工業。記憶體製造商為滿足市場對高速及儲存系統空 間持續成長的需求，採用先進的製程微縮、多階儲存等技術，以提升 密度以符合市場期待。雖然可以成功增加單位儲存空間及降低位元的 成本，同時也帶來可靠度的挑戰，例如:因電源突然中斷造成資料回 復議題，更高的位元錯誤率及錯誤分佈不均及持續降低的耐久度等。為了解決因電源突然中斷造成的資料回復議題，我們提出植基於晶片級容錯式磁碟陣列 (RAID)，藉由分散資料寫入位置，當資料寫入的過 程中若遭遇突然的斷電，可以保證資料的回復。為了解決因不同的邏輯頁的位元錯誤率的差異造成可靠度下降的問題，一個植基於正交錯誤更正與錯誤位置感知的寫入策略被提出來，可將錯誤攤平以延長快閃記憶體使用壽命。為了解決在相變化記憶體上，因傳統的抹平技術 與寫入資料導致位元翻轉不平均而使得部份的位元無法被充份利用， 一個植基於一次寫入記憶體編碼的寫入策略被提出，此策略不但可以抵抗資料的變化並保障位元翻轉平均，以避免部份位元提早損壞。 | zh_TW |
| dc.description.abstract | In past decade, non-volatile memory (e.g. flash memory and phase-change-memory) has been widely adopted in various domains of our life, from consumer electronics, personal computers, enterprise storage to the Internet of Things and the automotive industry. In order to meet the market demand for continuous growth of high-speed and storage space, memory manufacturers adopt advanced process shrinking, Multi-Level-Cell technique, and even three dimension architecture to successfully increase the chip capacity and reduce the cost per bit. However, in the meanwhile, it bring serious reliabil- ity challenges, for example, data corruption due to sudden-power-loss when programming, higher bit-error-rate, uneven distribution of errors, and continuous decreasing endurance. In order to solve the data corruption issue due to sudden-power-loss, we proposed a chip-level RAID design, a data-backup-free design, to guarantee the recovery of data via distributing the write data. In order to deal with the deteriorated reliability caused by difference between logical pages in TLC-flash memory, we proposed a orthogonal error-correcting-code based and error-locality aware design, error-leveling design, to level out the errors to extend the lifetime of TLC-based flash memory. In order to address the uneven bit-flips problem due to applying traditional wear-leveling mechanism and write data variation, we proposed a WOM- code-based programming strategy, bit-flip-leveling design, to resist data variation as well as guarantee the bit-flips to avoid some (hot) bits worn out earlier. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T14:34:39Z (GMT). No. of bitstreams: 1 ntu-107-D98922036-1.pdf: 4330133 bytes, checksum: 949f13a8fecf39439c107fd60d52bc1f (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 1 Introduction 1
2 Related Work 3 2.1 The Designs of Flash Translation Layer .................. 3 2.2 Error Correction Code and Wear Leveling ................. 4 2.3 RAID on FlashMemory .......................... 5 2.4 Write-Once-MemoryCode ......................... 6 3 A Chip-leveling Design 9 3.1 Motivation.................................. 9 3.2 Design Overview .............................. 10 3.3 Data-Backup-Free Programming Method ................. 13 3.4 Management Designs of Data-Backup-Free Programming Method . . . . 18 3.4.1 DBFP Manager........................... 18 3.4.2 Space Reclaimer .......................... 19 3.4.3 Recovery Handler ......................... 20 3.5 Performance Evaluation........................... 20 3.5.1 Experiment Setups ......................... 20 3.5.2 Experimental Results........................ 22 3.5.3 Read/Write Performance...................... 22 3.5.4 Overhead.............................. 24 4 An Error-leveling Design 27 4.1 Motivation.................................. 27 4.2 Design Overview .............................. 28 4.3 Mask and Freeze Procedure......................... 30 4.4 Performance Evaluation........................... 31 4.4.1 Evaluation Metrics and Experiment Setup . . . . . . . . . . . . . 31 4.4.2 Experimental Results........................ 33 5 A Bit-flip leveling Design 35 5.1 Motivation.................................. 35 5.2 Design Overview .............................. 36 5.2.1 Design Detail............................ 37 5.3 Performance Evaluation........................... 39 5.3.1 Experimental Setup......................... 39 5.3.2 Experimental Results........................ 40 6 Conclusion Remarks 43 Bibliography 44 Curriculum Vitae 53 Publication List 55 | |
| dc.language.iso | en | |
| dc.title | 非揮發性儲存裝置可靠度提升之寫入策略 | zh_TW |
| dc.title | Reliability-Enhanced Programming Styles for NVM Storage | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.coadvisor | 張原豪(Yuan-Hao Chang) | |
| dc.contributor.oralexamcommittee | 施吉昇(Chi-Sheng Shih),徐慰中(Wei-Chung Hsu),王克中(Ke-Chung Wang),洪士灝(Shih-Hao Hung) | |
| dc.subject.keyword | 非揮發性記憶體,快閃記憶體,相變化記憶體,錯誤更正碼,耐久度,可靠度,電源突然中斷, | zh_TW |
| dc.subject.keyword | non-volatile memory,flash memory,phase-change-memory,endurance,error-correcting-code,endurance,reliability,sudden-power-loss, | en |
| dc.relation.page | 56 | |
| dc.identifier.doi | 10.6342/NTU201801163 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-07-23 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2023-08-14 | - |
| 顯示於系所單位： | 資訊工程學系 | |
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