改善銅損缺陷在奈米級半導體金屬導線積體電路製程整合之研究

Abstract

隨著積體電路（integrated circuit, IC）的進步，半導體元件尺寸越來越小、導線層數急遽增加，使金屬導線 （interconnection） 線寬 （line width） 也要隨之縮小，元件的導線已經進入奈米化（nano-scale）的尺寸，其主要的目的在於降低因為積體電路高度元件積集度所產生的功率消耗與熱量，並大幅縮小其體積，以達成元件輕薄短小、提高功能與降低功率的可能。元件導線中的電阻及電容所造成的電阻-電容延遲時間效應（RC delay time effect），會嚴重影響到整體電路的運作速度，在半導體製程上，導線的電容與電阻性能決定了製程技術。要解決這個問題有二種方法:第一個是採用低電阻的銅金屬當導線材料；較早的半導體製程在線寬大於0.13微米（μm）採用鋁金屬為導線，而銅金屬的電阻比鋁還低了約三分之一。第二個是選用低介電常數材料（low-K dielectric）作為介電層之材料。改用銅金屬作電路導線，除了可以改善積體電路的傳輸效能，可以將性能提升30%~40%之多外，鋁製程是採用真空物理氣相沉積（physical vapor deposition，PVD）的方式，而銅製程是採用電鍍（electro copper plating, ECP）的方式將銅鍍在晶片上，因此銅製程可比鋁製程節省約三成左右的材料及製造成本。此外，銅金屬的抗電致遷移能力亦比鋁金屬好，可減少導線斷開的機率，大幅提高積體電路的可靠性。然而，雖然銅製程的優點多，但因銅對矽元素而言是活性金屬，很容易擴散到矽中，或是污染無塵室，因此在製程上比較麻煩，要更加小心。 隨著半導體銅製程技術進入線寬小於40 奈米（nanometer）世代，各線路之厚度及寬度皆急遽降低。隨著銅金屬導線結構微縮化（scaling down），因銅金屬的高活性產生的缺陷與缺點，也開始慢慢浮現，並影響到半導體元件的正常運作。更嚴重的是，此類缺陷通常是在製程完成初期並看不出異常，而是要經過一段時間的電壓操作（operation voltage）後才會出現，也就是我們所說的可靠度缺陷（reliability defect），因此在奈米世代，對於可靠度極限之了解與正確的描述其主要的失效機制是極為重要的。銅損（Copper loss）便是其中最嚴重的一種可靠度缺陷，在數個最先進的奈米世代中，都可以看到它的蹤跡，雖然都提出了改善的方法，但是在下一世代又會再度出現，可見銅損已經到了製程臨界點。 本論文中，將會針對在銅金屬製程中的各項過程步驟，對銅損的影響作探討，並透過特別設計的銅製程結構，藉著穿透式電子顯微鏡（TEM）、導線特性及產品良率，以期找出對銅損最好的改善方向與製程條件。

For RC delay concern, material of metal line was changed form Aluminum to Copper under 0.13um technology. The Copper metal process was called damascene technology which includes three different processes to Aluminum metal process: deposition for barrier and seed layers, copper electro-deposition, electro copper plating (ECP) and copper chemical mechanical planarization (CMP) With chip size and line width continuously shrinkage in advanced technology, metal line dimensional was shrunk to nanometer scale, and Cu voids in metal lines cause the failure of via-induced metal-island corrosion. It impacts not only yield loss but also device reliability, specifically electron migration (EM) and stress migration (SM). One of the Cu voids is located under via bottom which is more unpredictable than others due to hard to be detect by inline defect scan. The Cu void under via bottom is caused by integrated processes such as via dry etch and wet clean. It is not similar to the Cu void caused by barrier Cu-seed and ECP Cu. The mechanism of Cu voids under via bottom formation from dry etch and wet clean are related to Cu dual-damascene interconnection. Both plasma damage and chemical reaction are proposed to explain its failure mechanism. In the integrated process of Cu interconnects, we can design not only the safety dimension of Cu line via depth but also process criteria with less damage and oxidation in dry etching and wet clean based on Cu loss amount (Cu recess) in TEM inspection. EDS mapping for element detection in failure analysis was used to identify failed process stage, and high temperature operation life test was also used for reliability assessment. The modified actions for via bottom improve not only wafer yield but also reliability quality.