應用於無線區域網路IEEE 802.11ax 具晶格簡化輔助多輸入多輸出偵測器之遞迴式接收機設計

Abstract

無線區域網路802.11是一個成功且普及的無線通訊標準，隨著使用需求的提升，新一代的802.11ax提供更高的傳輸速率與效率，但需要支援高達1024-QAM調變。高維度之調變可透過多輸入多輸出偵測器使用晶格簡化搭配K最佳搜尋與Max-log目錄解映射器來實現，但晶格簡化會造成K最佳搜尋所需處理不規則搜尋樹，而每條搜尋路徑又難以快速計算。遞迴式偵測解碼器可藉由偵測器與解碼器之間的外部遞迴，交換軟式資訊來提升錯誤性能，但傳統之外部遞迴需進行完整偵測跟解碼，導致複雜度隨著外部遞迴次數等比例上升，無法滿足低運算延遲需求。本論文提出了文獻中第一個802.11ax相容的遞迴式偵測解碼接收機，可支援高達4x4 1024-QAM 調變的多天線系統。本設計採用硬體可實現之晶格化簡輔助K最佳偵測演算法，並提出一個實際可行的遞迴式偵測解碼器，可進一步改善封包錯誤率效能，且硬體成本與運算延遲不隨外部遞迴次數成正比。在符合802.11ax 所需資料傳輸率與運算延遲要求下，藉由分析錯誤效能、功耗與面積之可能設計進行最佳遞迴偵測解碼器設計。並使用外部資訊轉換圖分析，可節省50%的遞迴偵測解碼內部遞迴次數，但只損失0.05dB的封包錯誤率。本論文提出的遞迴偵測解碼器可支援802.11ax 4x4 MCS-11與160MHz頻寬並且在WLAN B、D、E通道下皆能滿足錯誤率要求，使用40nm CMOS製程設計，比起可實現之最佳無遞迴接收機可提升1dB的錯誤率效能，並且只需28%的晶片面積與30%的功率消耗。

The 802.11 wireless LAN (WLAN) standards have been successful and popular wireless communication solutions. The emerging 802.11ax can provide even higher data rates for increasing traffic demands by supporting up to 1024-QAM, introducing design challenges. Soft-input-soft-output (SISO) MIMO detection is implemented with lattice reduction aided (LRA) K-best search and a max-log list demapper to deal with such a high-order modulation. However, the search tree becomes irregular in the LRA-K-best algorithm, making the paths hard to traverse. The error rate performance can be improved by exchanging soft information between the MIMO detector and the error correction code (ECC) decoder by employing iterative detection and decoding (IDD). However, detection and decoding need to be performed in each outer iteration, resulting in an unacceptable processing time proportionally to the number of outer iterations. This work presents the first 802.11ax compliant IDD receiver that supports up to 4x4 1024-QAM MIMO detection in the open literatures. A hardware-feasible LRA-K-best detection algorithm is adopted to traverse paths efficiently. A practical IDD receiver, for which cost and latency are not proportional to the number of outer iterations, is used to further reduce the complexity and improve the packet-error-rate (PER) performance. Performance, power, and area (PPA) metrics are well evaluated to explore the design space and to identify the optimal 802.11ax compliant IDD receiver architecture. 50% of IDD inner iterations are reduced with only 0.05dB PER performance loss by leveraging the extrinsic information transfer (EXIT) chart. The proposed practical IDD receiver can support 802.11ax 4x4 MCS-11 with 160MHz channel bandwidth, and achieve the requirement PER performance in WLAN B, D and E channels. The proposed IDD receiver is designed in a 40nm CMOS technology. It improves the error performance by 1dB with only 28% chip area and 30% power consumption when compared to a feasible realization of the optimal non-IDD receiver.