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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭大維 | |
dc.contributor.author | Hung-Sheng Chang | en |
dc.contributor.author | 張弘昇 | zh_TW |
dc.date.accessioned | 2021-05-19T17:51:49Z | - |
dc.date.available | 2027-08-02 | |
dc.date.available | 2021-05-19T17:51:49Z | - |
dc.date.copyright | 2017-08-20 | |
dc.date.issued | 2017 | |
dc.date.submitted | 2017-08-03 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7737 | - |
dc.description.abstract | 近年來隨著快閃記憶體(NAND Flash)和相變化記憶體(PCM)的發展,非揮發性記憶體成為了未來系統設計中不可或缺的角色,然而,既有的記憶體階層架構並無法善用非揮發記憶體的優勢,因而產生出諸多的問題(可靠度,效能等),因此本論文提出一個高效率和高可靠度的記憶體階層架構來解決因為非揮發性記憶體的系統問題。首先,在底層的儲存裝置的部分,本論文針對三維堆疊的快閃記憶體提出一個降低寫入擾動的管理機制,藉由冷熱資料以及高低快閃記憶體頁面(High and low flash page)的可靠度差異性,來降低資料保存在低可靠度的區域被干擾的機會,進而建構出高可靠度的儲存記憶體架構,此外,本論文針對相變化記憶體提出一個高效率的快取記憶體架構,藉由硬體輔助的方式,降低追蹤資料存取特性所需的負擔,並且利用一個輕巧的群組式資料結構,讓髒以及熱的資料盡可能的保留在快取中,以改善過多寫入帶給相變化記憶體的耐久度和效能的問題。本論文最後針對未來未來三維堆疊化的相變化記憶體所帶來的資料持久度問題提出一個高可靠度的管理機制,這個機制主要是在不同溫度和資料特性下,藉由合適的寫入方式來改善三維堆疊化的資料持久度的問題。最後,我們採用一連串的實驗來驗證所提方法之效能,並展示出所提之架構設計的可行性。 | zh_TW |
dc.description.abstract | With the fast developing of NAND flash memory and phase change memory (PCM), non-volatile memories (NVM) have played the important role in the system design. However, the existing memory hierarchy does not consider the characteristics of NVM so as to introduce many challenges, such as reliability and performance issues. Thus, this dissertation proposes an efficient and reliable memory hierarchy to resolve the issues when the system adopting NVM. First, in the storage memory hierarchy, this dissertation proposes a program disturbance-aware management for 3D-based NAND flash memory. This management exploits the features of hot/cold data and the characteristics of high/low pages to construct a highly reliable storage architecture. In addition, in the main memory hierarchy, this dissertation proposes a lightweight software-controlled cache architecture to mitigate the performance gap between SRAM cache and NVM-based main memory. In this cache, this dissertation exploits the hardware-assistance to reduce the overhead to track the data hotness. Meanwhile, this dissertation designs a lightweight group-based data structure to keep the hot and dirty data on the cache. Thus, the performance and endurance issue of PCM could be significantly mitigated by adopting the proposed cache architecture. Finally, we proposes a reliable main memory hierarchy by designing a retention-aware management for future 3D-based PCM. This management exploits the temperature and program iterations to improve the retention issue of 3D-based PCM. Finally, these managements have evaluated by a series experiments and show the corresponding practicality of the proposed design. | en |
dc.description.provenance | Made available in DSpace on 2021-05-19T17:51:49Z (GMT). No. of bitstreams: 1 ntu-106-D01922003-1.pdf: 1517576 bytes, checksum: a0f43b52d142c76f4b4186c7ca295a08 (MD5) Previous issue date: 2017 | en |
dc.description.tableofcontents | Contents
Abstract in Chinese iii Abstract v Acknowledgement vii List of Figures xiii List of Tables xiv 1 Introduction 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1 Research Issues on Flash Memory . . . . . . . . . . . . . . . . . 4 1.3.2 Research Issues on Phase Change Memory . . . . . . . . . . . . 5 1.4 Objectives and Contributions . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 A Reliable Sub-Block Design for NVM-based Storage 10 2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Proposed Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 Disturbance-aware Sub-Blocks . . . . . . . . . . . . . . . . . . . 16 2.2.3 Disturbance-aware Free Sub-Block Allocation with Hot/Cold Data Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.2 Experiment Results . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 An Ef.cient Cache Design for NVM-based Main Memory 30 3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 Proposed Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.2 Coarse-Grained Management Data . . . . . . . . . . . . . . . . . 37 3.2.3 Access-Pattern-Aware Cache Management . . . . . . . . . . . . 38 3.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.1 Performance Metrics and Experiment Setup . . . . . . . . . . . . 42 3.3.2 Experiment Results . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.3 Con.guration Considerations . . . . . . . . . . . . . . . . . . . 47 3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4 A Reliable Design for NVM-based Main Memory 52 4.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2 Proposed Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.2 Hot Data Tracking Component . . . . . . . . . . . . . . . . . . . 57 4.2.3 Container-based Design for Hot SubArea . . . . . . . . . . . . . 59 4.2.4 Coarse-granularity Management . . . . . . . . . . . . . . . . . . 63 4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.1 Performance Metrics and Experiment Setup . . . . . . . . . . . . 66 4.3.2 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . 67 4.3.3 Detail Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5 Concluding Remarks 71 5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Bibliography 75 Curriculum Vitae 83 Publication List 85 | |
dc.language.iso | en | |
dc.title | 記憶體階層下之非揮發性記憶體使用 | zh_TW |
dc.title | Exploring the Usage of Non-Volatile Memories with the Consideration of Memory Hierarchy | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-2 | |
dc.description.degree | 博士 | |
dc.contributor.coadvisor | 張原豪 | |
dc.contributor.oralexamcommittee | 王克中,施吉昇,薛智文,洪士灝,楊佳玲 | |
dc.subject.keyword | 快閃記憶體,相變化記憶體,儲存系統,快取系統,記憶體系統, | zh_TW |
dc.subject.keyword | Flash Memory,Phase Change Memory,Storage System,Cache System,Main Memory System, | en |
dc.relation.page | 88 | |
dc.identifier.doi | 10.6342/NTU201701489 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2017-08-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
dc.date.embargo-lift | 2027-08-02 | - |
顯示於系所單位: | 資訊工程學系 |
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