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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77298| 標題: | 應用於 Ka 頻段之微波發射器與功率放大器之設計 Design of Microwave Transmitter and Power Amplifier for Ka-band Applications |
| 作者: | 黃彥儒 Yen-Ju Huang |
| 指導教授: | 黃天偉 Tian-Wei Huang |
| 關鍵字: | 互補式金屬氧化物半導體,5G 無線系統,衛星通訊,功率放大器,微波發射器, CMOS process,5G communication system,Satellite Communucation,Power Amplifier,Microwave Transmitter, |
| 出版年 : | 2019 |
| 學位: | 碩士 |
| 摘要: | 目前隨著第五代行動通訊與衛星通訊的發展,對於更高頻寬與傳輸速率的需求與日俱增,因此射頻領域操作頻率的趨勢皆轉向於毫米波的研究與應用。其中,在第五代行動通訊中,多數國家除了sub-6GHz的使用外,在更高頻率中,皆將28 GHz與38 GHz設定為未來實際應用的頻段。而19 GHz及29 GHz則為衛星通訊的主要使用頻段。在無線通訊系統中,收發機的設計扮演著相當重要的部分,在本篇論文中,將著重於發射器關鍵元件的設計。
本篇論文主要分為兩個部分:第一部分(第二章)為一個應用於Ka頻段的衛星通訊之功率放大器。該功率放大器以180 nm CMOS製程實現,架構上採用疊接組態作為單元,並使用兩級與兩路combine的設計,以讓該電路能達到較高的輸出功率。其中,匹配網路以集總元件來完成,藉以有效縮小晶片面積。性能上,在29兆赫茲的操作頻率之下此功率放大器的飽和輸出功率為15.7 dBm,並提供19.2 dB之小訊號增益。1dB壓縮輸出功率點為12.7 dBm以及最大功率附加效率達12.5%。 第二部分(第三章),則為一個設計於38 GHz的輻射狀之功率放大器搭配被動式環形混頻器的三維結構之發射器。該發射器使用65 um CMOS製程實現。該發射器在混頻器中選用被動式環形混頻器設計,以利面積縮小與良好線性度。功率放大器的部分則是使用輻射狀的架構,該架構可達到良好的電路布局對稱性與縮小面積,故可擁有良好的單位輸出功率密度。性能上,由於電路有頻移現象,因此中心頻率位於24GHz。在24GHz的轉換增益達3 dB,1dB壓縮輸出功率點與飽和輸出功率分別為1 dBm、5.5 dBm。IF頻寬在LO頻率為25.9 GHz時可達1.2 GHz。 Nowadays, with the development of the fifth-generation mobile communication (5G) and satellite communication, there are increasing demand of broadband and higher transmission rate. As a result, the research and application of millimeter wave has gradually become the trend recent years. For the fifth-generation mobile communication, most of nations have set not only sub-6 GHz but also millimeter wave, such as 28 GHz or 38 GHz, as their bands to use. For satellite communication, 19 GHz and 29 GHz are the main frequency bands. In wireless communication systems, the design of the transceiver plays a quite important role. This thesis focuses on the design of key components of the transmitter. This thesis is divided into two parts. In the first part (Chapter 2), a Ka-band power amplifier for satellite communication systems is presented. The proposed PA is fabricated in 180nm CMOS process provided by TSMC. The proposed PA utilizes cascode configuration as a cell, comprises two cascade stage and two-way combined in second stage to achieve higher output power. Also, matching networks completed by lumped-elements can make chip size minimization. The total performance of this PA achieves Psat of 15.7 dBm with 12.5% PAEmax and OP1dB of 12.7 dBm and attains the small signal gain of 19.2 dB at 29 GHz. The second part of the thesis is the proposed 3D radial architecture 38 GHz transmitter. The proposed transmitter fabricated in 65nm CMOS process provided by TSMC. The mixer part adopts the passive ring mixer for chip size minimization and higher linearity. Also, the radial architecture power amplifier is adopted for symmetry layout. The proposed architecture can achieve excellent power area density. Under the measurement, the center frequency of the circuit shifts from 38 GHz to 24 GHz. At 24GHz, the conversion attains 3 dB, the OP1dB achieves 1 dBm and the Psat is around 5.5 dBm. Moreover, the 3-dB IF bandwidth has 1.2 GHz when LO frequency is 25.9 GHz. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77298 |
| DOI: | 10.6342/NTU201902294 |
| 全文授權: | 未授權 |
| 顯示於系所單位: | 電信工程學研究所 |
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| ntu-107-2.pdf 未授權公開取用 | 2.79 MB | Adobe PDF |
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