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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳敏璋 | zh_TW |
| dc.contributor.author | 林昱廷 | zh_TW |
| dc.contributor.author | Yu-Ting Lin | en |
| dc.date.accessioned | 2021-07-10T21:49:32Z | - |
| dc.date.available | 2024-08-20 | - |
| dc.date.copyright | 2019-08-23 | - |
| dc.date.issued | 2019 | - |
| dc.date.submitted | 2002-01-01 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77177 | - |
| dc.description.abstract | 本論文主要在研究電漿處理對原子層沉積技術(Atomic layer deposition, ALD)的影響。在 thermal mode ALD中加入電漿處理後，發現薄膜厚度有被抑制的效果。本研究進一步將電漿處理應用於高介電係數介電層的製程中，經電漿處理後的金屬氧化物半導體(metal-oxide-semiconductor, MOS)電容元件，相較於一般thermal mode ALD製程，有明顯不同的電性表現，可以有效提升MOS電容元件的電容並降低其漏電流。透過X光反射(X-ray reflectivity)圖譜的分析可以發現，經由電漿處理的高介電係數介電層具有較高的薄膜密度。此外，X射線光電子能譜(X-ray photoemission spectroscopy)的量測指出，電漿處理可以降低高介電係數介電薄膜中的氧空缺含量。藉由thermal mode ALD技術與電漿處理的進一步優化，可以達到MOS電容元件最佳之電性表現目標。 | zh_TW |
| dc.description.abstract | This thesis focuses on the effect of plasma treatment on the atomic layer deposition (ALD) process. The growth rate of the ALD process is suppressed by the plasma treatment. In addition, the plasma treatment contributes to significant impact on electrical properties of high-K gate dielectrics in metal-oxide-semiconductor (MOS) capacitors. The high-K gate dielectric treated by the plasma treatment exhibits a superior performance than that prepared by the thermal mode ALD process. The capacitance is enhanced and the leakage current is reduced significantly by the plasma treatment, which is ascribed to the film densification as revealed by the X-ray reflectivity. The X-ray photoemission spectroscopy analysis indicates that the oxygen is suppressed by the plasma treatment. The optimization of the thermal mode ALD process and the plasma treatment leads to the significant enhancement of the electrical performance of MOS capacitors. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-10T21:49:32Z (GMT). No. of bitstreams: 1 ntu-108-R06527063-1.pdf: 3205861 bytes, checksum: 0fb0a59f58fc4814cb2135370dec23a4 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 致謝 I
摘要 II Abstract III 目錄 IV 圖目錄 VI 表目錄 IX 第 1 章 簡介 1 1.1 原子層沉積技術 1 1.1.1 原子層沉積技術 1 1.1.2 電漿輔助原子層沉積技術 8 1.2 高介電係數材料 13 1.3 量測儀器簡介 15 1.3.1 X光光電子能譜儀(X-ray Photoemission Spectroscopy, XPS) 15 1.3.2 橢圓偏振儀(Spectroscopic Ellipsometry, SE) 16 1.3.3 低掠角X光繞射(Grazing Incident X-ray Diffraction, GIXRD) 17 1.3.4 X光反射率(X-ray Reflectivity) 19 第 2 章 原子層技術用於高介電材料閘極介電層之效能增強 21 2.1 研究動機 21 2.2 實驗步驟 23 2.2.1 前驅物介紹 29 2.3 實驗結果與討論 29 2.3.1 薄膜厚度分析 29 2.3.2 XRR密度分析 32 2.3.3 AFM薄膜平整度分析 37 2.3.4 薄膜MOS/MIM電性分析 37 2.3.5 XPS interfacial layer分析 57 2.3.6 TEM cross section分析 69 2.4 結論 71 參考資料 72 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 金屬氧化物半導體電容元件 | zh_TW |
| dc.subject | 高介電係數介電層 | zh_TW |
| dc.subject | 電漿處理 | zh_TW |
| dc.subject | 原子層沉積技術 | zh_TW |
| dc.subject | plasma treatment | en |
| dc.subject | high-K gate dielectrics | en |
| dc.subject | atomic layer deposition (ALD) | en |
| dc.subject | metal-oxide-semiconductor (MOS) capacitors | en |
| dc.title | 原子層技術應用於High-k閘極介電層效能增強之研究 | zh_TW |
| dc.title | Atomic Layer Technology For Performance Enhancement of High-K Gate Dielectrics | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 107-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 胡振國;林新智;謝宗霖 | zh_TW |
| dc.contributor.oralexamcommittee | ;; | en |
| dc.subject.keyword | 金屬氧化物半導體電容元件,原子層沉積技術,高介電係數介電層,電漿處理, | zh_TW |
| dc.subject.keyword | metal-oxide-semiconductor (MOS) capacitors,atomic layer deposition (ALD),high-K gate dielectrics,plasma treatment, | en |
| dc.relation.page | 74 | - |
| dc.identifier.doi | 10.6342/NTU201903233 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2019-08-19 | - |
| dc.contributor.author-college | 工學院 | - |
| dc.contributor.author-dept | 材料科學與工程學系 | - |
| 顯示於系所單位： | 材料科學與工程學系 | |
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