化學氣相沉積成長之垂直堆疊鍺錫/鍺矽通道閘極環繞式電晶體之製備與特性分析

Abstract

在本篇論文中著重於化學氣相沉積成長之鍺錫量子井p型金氧半場效電晶體與垂直堆疊鍺錫p型/鍺矽n型閘極環繞式電晶體之製備與特性分析，分別探討磊晶層結構設計、材料分析、電子束曝光、非等相性蝕刻、通道生成、閘極堆疊、源汲極接觸、電流-電壓/電容-電壓特性分析、變溫量測、介面缺陷密度萃取、外部應力響應、低頻雜訊與穿透式電子顯微鏡分析之相關模組技術與製程整合。 閘極環繞式結構有著最佳之閘極控制能力。垂直堆疊通道可於一給定面積之下增加等效通道寬度進而增進電流。垂直堆疊奈米片於一給定面積下有相較垂直堆疊奈米線與鰭式電晶體著更大之導通電流與更小之寄生電容。此外垂直堆疊奈米片相較於鰭式電晶體在先進製程能力上有著許多優勢。首先，良好控制之磊晶、選擇性等相性蝕刻與原子層沉積造成高一致性的奈米片厚度的並具有小的表面粗糙度與較鰭式電晶體小的通道間隔。此外，於奈米片下方之應力釋放層可以提供強大之應力來源。再者，可依照設計需求與極紫外光技術調整垂直堆疊奈米片之等效通道寬度而增加設計靈活性與佈局效率。另一方面，鍺矽、鍺與鍺錫之鍺基通道可利用化學氣相沉積磊晶成長於矽基板上並有較矽而言更大之載子遷移率，故成為有機會取代矽之候選材料。 本論文之第一部分將探討最佳化鍺覆蓋層厚度於鍺錫量子井p型金氧半場效電晶體中。鍺覆蓋層於鍺錫通道上可以降低介面缺陷密度並且將載子遠離氧化層/鍺之介面進而降低雜質散射與表面粗糙度散射以增進載子遷移率。然而，若鍺覆蓋層厚度太厚，則會有許多載子位於鍺覆蓋層中，而導致載子遷移率下降。1奈米鍺覆蓋層於鍺錫通道上可達成化學氣象沉積成長之鍺錫p型電晶體之世界紀錄電洞遷移率509 cm2/V·s。 本論文之第二部分探討利用最佳化雙氧水濕式蝕刻之通道生成條件、低熱預算閘極、源汲極鉑鍺錫接觸於硼內摻雜鍺錫上，進而製備出世界第一顆垂直堆疊鍺錫通道p型閘極環繞式電晶體；此外利用不同方向之蝕刻速率差異性製備出具有{111}面之垂直堆疊三角形鍺0.91錫0.09通道可增進鍺錫通道p型閘極環繞式電晶體之效能；再者利用鍺0.95錫0.05覆蓋層於垂直堆疊鍺0.88錫0.12通道上、通道長度縮小至40奈米、壓縮應力增至3.3%、低通道摻雜、高源汲極摻雜與400oC之熱穩定性更進一步提升垂直堆疊鍺錫通道p型閘極環繞式電晶體之效能。此垂直堆疊鍺0.88錫0.12奈米片具有所有鍺錫P型電晶體中世界紀錄之58A每通道堆疊導通電流 (2724 μA/μm 每單位通道水平寬度導通電流或376 μA/μm 每單位通道周長導通電流)於VOV=VDS= -0.5V，與世界紀錄之172S每通道堆疊最大跨導 (8037 μS/μm 每單位通道水平寬度最大跨導或1110 μS/μm 每單位通道周長最大跨導)於VDS= -0.5V；此外，利用自由基蝕刻為基礎之高度選擇性等向性乾式蝕刻首次製備出4層堆疊12奈米厚之鍺0.915錫0.085通道p型閘極環繞式電晶體並具有大於50奈米之奈米片寬度、高源汲極摻雜與未摻雜通道。此乾蝕刻之蝕刻選擇比與均勻度相較於雙氧水濕蝕刻有非常顯著之提升。 本論文之最後部分將探討利用蝕刻最佳化去除寄生通道並製備具有0.27%拉伸應力之垂直堆疊鍺0.98矽0.02 n型閘極環繞式電晶體。為了要選擇性蝕刻去除寄生矽通道、鍺緩衝層、鍺犧牲層並保留鍺矽通道，鍺矽通道有著2%之矽。而因為只有2%，此鍺矽通道之導帶中L谷能量還是所有谷中最小的，且合金散射非常小，故可以有著較大之載子遷移率，達成14.9A每通道堆疊導通電流 (1250 μA/μm 每單位通道水平寬度導通電流或211 μA/μm 每單位通道周長導通電流)於VOV=VDS= -0.5V，與39.4μS每通道堆疊最大跨導(3280 μS/μm 每單位通道水平寬度最大跨導或559μS/μm每單位通道周長最大跨導)於VDS= -0.5V並具備次臨界擺幅=73mV/dec。

In this dissertation, the fabrication and characterization of chemical vapor deposition (CVD)-grown GeSn quantum well (QW) pMOSFETs and vertically stacked GeSn p-type Gate-All-Around (GAA) FETs/GeSi nGAAFETs are investigated in terms of epi structure design, material analysis, e-beam lithography, anisotropic etching, channel release, gate stack, SD contact, IV/CV characteristics, temperature dependent measurement, interface trap density (Dit) extraction, external strain response, low frequency noise, and TEM analysis. GAA structure has the ultimate gate controllability. Stacked channel structure enlarges effective channel width (channel perimeter, Weff) in a given footprint to improve ION. Stacked nanosheets has larger ION and smaller parasitic capacitance than stacked nanowires and FinFETs in a certain footprint. There are many benefits for stacked nanosheets as compared to FinFETs in points of advanced process capability. First of all, the well-controlled epitaxy, selective isotropic etching, and atomic layer deposition (ALD) process result in uniform nanosheet thickness with small surface roughness and small inter-channel spacing. In addition, the strained relaxed buffer (SRB) under the nanosheets can be a strong stressor. Moreover, continuous Weff tuning of stacked nanosheets and EUV technology add design flexibility and improve layout efficiency. On the other hand, the Ge-based channel materials, such as GeSi, Ge, and GeSn, can be epitaxially grown on Si wafer by CVD with higher mobility than Si, becoming promising candidates to replace Si. In the first part of this dissertation, GeSn QW p-MOSFETs are demonstrated with optimized Ge cap thickness. The Ge cap on the GeSn channel can reduce the interface trap density (Dit) and also separate the carriers from the oxide/Ge interface to reduce the impurity scattering and surface roughness scattering for high mobility. However, the mobility also degrades with thick Ge cap due to the large hole population in the Ge cap. The GeSn with 1nm Ge cap achieve the record high peak mobility of 509 cm2/V·s among all CVD-grown GeSn pFETs. In the second part of this dissertation, the first stacked GeSn pGAAFETs are demonstrated by optimized channel release process of H2O2 wet etching, low thermal budget gate stack, and S/D PtGeSn contact on in-situ B doped GeSn. In addition, the performance enhancement for GeSn pGAAFETs are demonstrated by the stacked triangular Ge0.91Sn0.09 Channels with {111} facets formed by orientation dependent etching. Moreover, the performance of stacked GeSn pGAAFETs are further boosted by stacked Ge0.88Sn0.12 channels with Ge0.95Sn0.05 cap, scaled gate length (Lg)=40nm, enlarged compressive strain of 3.3%, low channel doping, and high S/D doping with thermal stability up to 400oC. The stacked 3 Ge0.88Sn0.12 nanosheets achieve record ION of 58μA per stack (2724μA/μm per channel footprint (WCH or 376μA/μm per Weff) at VOV=VDS= -0.5V and record Gm,max of 172μS (8037μA/μS per WCH or 1110 μA/μS per Weff) at VDS= -0.5V among all GeSn pFETs. Furthermore, the first 4-stacked, 12nm-thick Ge0.915Sn0.085 with the width larger than 50nm, high S/D doping and undoped channels are realized by a radical-based highly selective isotropic dry etching (HiSIDE). The etching selectivity and the channel uniformity are highly improved by the dry etching as compared to H2O2 wet etching. In the final part of this dissertation, the stacked 0.27% tensily strained Ge0.98Si0.02 nGAAFETs are fabricated without parasitic channels by optimized etching process. To selectively etch the parasitic Si, Ge buffer, and Ge sacrificial layers (SL) over the GeSi channels, the GeSi channels have 2% Si inside. The Ge0.98Si0.02 still has L valleys as the conduction band minima and very weak alloy scattering for high mobility. ION of 14.9μA per stack (1250μA/μm per WCH or 211μA/μm per Weff) at VOV=VDS=0.5V and Gm,max of 39.4μS per stack (3280μS/μm per WCH or 559μS/μm per Weff) at VDS =0.5V with SS=73mV/dec are achieved.