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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76990完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳怡然(Yi-Jan Emery Chen) | |
| dc.contributor.author | Yi-Ting Lin | en |
| dc.contributor.author | 林奕廷 | zh_TW |
| dc.date.accessioned | 2021-07-10T21:42:39Z | - |
| dc.date.available | 2021-07-10T21:42:39Z | - |
| dc.date.copyright | 2020-08-04 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-07-29 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76990 | - |
| dc.description.abstract | 中文摘要 ________________________________________ 本論文提出使用頻率倍率計算器數位式頻率合成器，除了延遲線、數位控制振盪器和除頻器，其餘的電路皆用數位標準元件庫來合成與佈局實現。頻率倍率計算器運用統計的特性來突破製程所能提供的最小時間解析度—單一個反相器的延遲時間，並具有較好的抵抗製程變異之能力。若在不考慮面積和功率消耗的情況下，根據數學模型可推論時間解析度能透過增加樣本數來大幅度地提升。頻率倍率計算器的輸出頻率倍率值為5位元整數和10位元分數代表，在參考頻率為30 MHz下，最小能表示的頻率解析度約為29.3 kHz，當取樣窗口為7週期時，倍率值解析度約為1.116×10-3，輸出的倍率值準確度為±0.01以內。 本論文提出的數位式頻率合成器使用0.18微米CMOS製程實現，晶片面積為1.149 × 0.781 mm2。頻率倍率計算器具有大的動態範圍，而採用環形架構的數位控制振盪器。在1.8 V供應電壓下，頻率控制編碼(FCW)由5位元整數和10位元分數所組成，其頻率合成器的頻率範圍為0.63-2.34 GHz，以及頻率合成器的解析度為117.2 kHz，功率消耗為30.9-100.8 mW，並且能達到分數型合成。於鎖定流程中加入了快速鎖定技術、粗略/細微調節以及鎖定階段控制電路來加速鎖定動作，量測結果跳頻288 MHz下，只需要2.5微秒的鎖定時間達到±100 ppm以內。 關鍵字：數位式頻率合成器、頻率倍率計算器、數位控制環形振盪器、快速鎖定 | zh_TW |
| dc.description.abstract | ABSTRACT ________________________________________ In this thesis, a digital frequency synthesizer by utilizing the Frequency Ratio Calculator (FRC) is proposed. The circuit is implemented by digital standard cell library, except delay line, dividers and digitally controlled oscillator. Based on the derived model and system architecture, the proposed FRC achieves high resolution in quantization and reveals fully insensitive characteristics against device/process variation of fabrication technology. The minimum resolution is not restricted to minimum gate delay of inverter chain available in a process technology. Furthermore, according to the mathematical model, the resolution of proposed FRC can be improved significantly by increasing the number of samples, without considering area and power consumption. The output frequency ratio of the FRC is a 5-bit integer and 10-bit fractional. The minimum frequency can be expressed of FRC is 29.3 kHz when the reference frequency is 30 MHz. When the window is selected to 7 periods, the ratio resolution is 1.116×10-3 and the accuracy of the output ratio is within ±0.01. The FRC is fabricated in 0.18 'μm' CMOS technology and the chip size is 1.149 × 0.781 mm2. The digitally controlled oscillator adopts ring type architecture because the FRC features a wide dynamic range. The frequency control words(FCW) is consisted of 5-bit integer and 10-bit fractional. The power supply of the chip is 1.8 V and the synthesizer’s power consumption is 30.9 to 100.8 mW for the output frequency is from 0.63 to 2.34 GHz and the synthesizer resolution is 117.2 kHz. Besides, the synthesizer achieves fraction-N synthesis. The fast locking technique, coarse/fine adjustment and locking stage controller are added to accelerate the locking. The measurement settling time shows that a step of 288 MHz is performed in 2.5 μs within ±100 ppm from the final frequency value. Index Terms ─ Digital Frequency Synthesizer, Frequency Ratio Calculator, Digitally controlled Oscillator, Fast Locking Technique | en |
| dc.description.provenance | Made available in DSpace on 2021-07-10T21:42:39Z (GMT). No. of bitstreams: 1 U0001-2907202010470000.pdf: 5831584 bytes, checksum: 8f8a4d67b2e27a6e0f4a62436bd67f7c (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 目錄 ________________________________________ 中文摘要 I ABSTRACT II 目錄 III 圖目錄 V 表格目錄 X Chapter 1 緒論 1 1.1 研究動機 1 1.2 論文架構 2 Chapter 2 鎖相迴路簡介 3 2.1 類比式鎖相迴路簡介 3 2.2 數位式鎖相迴路簡介 6 2.2.1 數位鎖相迴路—採用除頻器架構 7 2.2.2 數位鎖相迴路—不採用除頻器架構 9 2.2.3 時間數位轉換器簡介 12 2.3 文獻回顧 16 Chapter 3 頻率倍率計算器 36 3.1 頻率倍率計算器模型 36 3.2 頻率倍率計算器架構設計 44 3.2.1 平行化架構與延遲線 44 3.2.2 切換邏輯計數電路 48 3.2.3 整數區間判斷電路 51 3.2.4 頻率倍率計算器架構 52 3.3 頻率倍率計算器行為模擬 53 3.4 頻率倍率計算器與時間數位轉換器的差異 60 Chapter 4 使用頻率倍率計算器的數位式頻率合成器 62 4.1 數位式頻率合成器系統架構設計 62 4.2 數位式頻率合成器電路區塊 65 4.2.1 數位控制環形振盪器 65 4.2.2 數位迴路濾波器 69 4.2.3 鎖定階段控制電路 71 4.2.4 除頻器 73 4.3 電路模擬結果 74 4.4 晶片佈局及腳位說明 77 Chapter 5 晶片量測 80 5.1 晶片製作與印刷電路板設計 80 5.2 量測環境 87 5.3 量測結果 88 5.3.1 數位控制環形振盪器 88 5.3.2 數位式頻率合成器 93 5.4 討論 104 Chapter 6 結論 106 參考文獻 107 | |
| dc.language.iso | zh-TW | |
| dc.subject | 數位控制環形振盪器 | zh_TW |
| dc.subject | 頻率倍率計算器 | zh_TW |
| dc.subject | 快速鎖定 | zh_TW |
| dc.subject | 數位式頻率合成器 | zh_TW |
| dc.subject | Fast Locking Technique | en |
| dc.subject | Digital Frequency Synthesizer | en |
| dc.subject | Digitally controlled Oscillator | en |
| dc.subject | Frequency Ratio Calculator | en |
| dc.title | 使用頻率倍率計算器的0.18 µm CMOS數位式頻率合成器 | zh_TW |
| dc.title | A 0.18 µm CMOS Digital Frequency Synthesizer Using Frequency Ratio Calculator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃育賢(Yuh-Shyan Hwang),姚嘉瑜(Chia-Yu Yao),劉宗德(Tsung-Te Liu) | |
| dc.subject.keyword | 數位式頻率合成器,頻率倍率計算器,數位控制環形振盪器,快速鎖定, | zh_TW |
| dc.subject.keyword | Digital Frequency Synthesizer,Frequency Ratio Calculator,Digitally controlled Oscillator,Fast Locking Technique, | en |
| dc.relation.page | 111 | |
| dc.identifier.doi | 10.6342/NTU202002022 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2020-07-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| U0001-2907202010470000.pdf 未授權公開取用 | 5.69 MB | Adobe PDF |
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