佔兩電晶體面積之高密度靜態隨機存取記憶體與鍺光偵測器元件模擬

Abstract

半導體產業之技術節點一向依循著摩爾定律，透過縮小電晶體尺寸以達到更高效能的元件，為了克服尺寸微縮困境如短通道效應，三維結構之電晶體如：鰭式場效電晶體 (FinFET) 與環繞式閘極場效電晶體 (GAAFET) 相繼被提出，提供更佳的閘極控制能力以降低元件功耗。隨著人工智慧、物聯網及自動駕駛的發展，電腦高速運算能力的需求增加，製作出高效能及低功耗的元件為當務之急，而單晶片上的高速記憶體扮演重要的角色，在現今系統單晶片及處理器中，靜態隨機存取記憶體 (static random access memory, SRAM) 佔據了高達八成的面積，因此若能有效降低記憶體單元面積，便可在有限面積下塞入更多記憶體單元，以達到更高效能的需求。 本論文第一部分提出一嶄新的結構以應用於高密度六電晶體靜態隨機存取記憶體 (6T-SRAM)，並做設計與技術協同最佳化 (design technology co-optimization, DTCO) 來延續記憶體微縮，將四個N型垂直環繞式閘極場效電晶體堆疊於兩個P型鰭式場效電晶體，達到只佔兩電晶體面積 (2T) 之單元面積，因此稱之為佔兩電晶體面積之靜態隨機存取記憶體 (2T (footprint) SRAM)，並建構完整的製程模擬來探討其結構之可行性。根據台積電7奈米與5奈米節點設計規則，記憶體單元面積分別可達到0.0192與0.0168平方微米，與其他研究團隊相比，佔兩電晶體面積之靜態隨機存取記憶體在同一節點下皆擁有最小的面積。 此結構最大的優勢是可以在不影響單元面積下，藉由調整P型鰭式場效電晶體鰭的高度與N型垂直環繞式閘極場效電晶體的通道長度來控制P型電晶體與N型電晶體的電流強度。隨著電晶體持續微縮，製程變異對元件的影響變得無法忽略，因此，我們在元件模擬中也考量了閘極金屬功函數變異，模擬佔兩電晶體面積之靜態隨機存取記憶體之寫入與讀取的靜態雜訊邊界 (static noise margin, SNM)，並將其做結構優化，進而找出最低工作電壓，再透過優化電晶體之臨界電壓達到更低的工作電壓，模擬結果顯示，佔兩電晶體面積之靜態隨機存取記憶體擁有極佳的最低工作電壓，並有最小的單元面積，因此可作為未來次五奈米節點之高靜態隨機存取記憶體的候選方案。 高速運算的目標之一是應用於自動駕駛，而光達具有高解析度與高偵測距離等優點，是未來實現自動駕駛的關鍵。因此，要偵測光達所發射出的雷射光，就需要好的光偵測器，而四族的鍺材料在1310/1550奈米有較高的吸收係數，並擁有低成本可與半導體製程相容等特性，成為未來光偵測器的候選材料之一。 本論文第二部分，利用磊晶於矽基板上成長p-i-n結構的鍺光偵測器，然而實驗量得截止頻寬 (3-dB bandwidth) 太低無法作為高速元件，因此模擬光生成 (optical generation) 與光響應 (photoresponse) 來探討頻寬受限的原因。模擬結果發現，消除元件大面積造成的RC限制與空乏區外的擴散電流限制可大幅改善頻寬。由於鍺直接長在矽材料上會有晶格常數不匹配的問題，因此先長一較厚的鍺緩衝層，將缺陷控制在矽鍺接面處來降低元件暗電流，達到低雜訊的應用，此外，需減少低摻雜層的載子濃度來抑制擴散電流，綜合以上所述，利用 n-i-p 結構與重摻雜P型鍺緩衝層來製作鍺光偵測器，可同時達到提高截止頻寬與降低暗電流的效果。

The technology trend of the semiconductor industry has always followed Moore's law to enhance the performance of field-effect transistors (FETs) by continuously scaling down the feature size. To overcome the scaling challenge like short-channel effects (SCE), 3D transistors such as FinFETs and gate-all-around FETs (GAAFETs) have been proposed to improve the gate electrostatic controllability. With the rising of high-speed computing in artificial intelligence (AI), internet of things (IoT), and autonomous vehicles, high performance and low power devices are necessary. More on-chip memory is required to meet the performance and throughput requirements. Up to 80% of the chip area in modern system on chip (SoC) and processors is occupied by static random access memory (SRAM). Therefore, the demand on SRAM size reduction becomes indispensable for high performance application. In the first part of this thesis, the design technology co-optimization (DTCO) for SRAM scaling is demonstrated by a novel architecture of high density 6T-SRAM named 2T (footprint) SRAM, which has only two transistors footprint constructed by stacking four n-type vertical GAA transistors (VFETs) on two pFinFETs. A completed process simulation to fabricate 2×2 SRAM cell array is established. The local interconnects inside the 2T (footprint) SRAM cell are all implemented within the bottom pFinFETs footprint. The bitcell area of 0.0192 m2 and 0.0168 m2 are achieved for 7 nm and 5 nm nodes, respectively, which are the smallest SRAM size as compared to other works. The advantage of 2T (footprint) SRAM is that SRAM transistor sizing can be controlled by adjusting the fin height (Hfin) of pFinFET and the gate length (Lgn) of nVFET without increasing the bitcell area. To investigate the read/write stability, the static noise margin (SNM) is analyzed considering the work function variation (WFV) as the dominant VT variation source. Lgn and Hfin is optimized by finding the minimum operating voltage (Vmin). VT retargeting by engineering work function of metal gate can further reduce Vmin resulting in Vmin of 0.58 V. 2T (footprint) SRAM has the smallest bitcell area with comparable Vmin at 5 nm node. Therefore, it becomes a promising candidate of high density SRAM for 5 nm node and beyond. One of the purposes of high-speed computing is autonomous driving. Light detection and ranging (LiDAR) is necessary for high resolution and long range detection Therefore, the development of photodetectors is required. Germanium (Ge) photodetectors become one of the candidates due to high optical absorption, low cost, and compatibility with complementary metal-oxide-semiconductor (CMOS) process. In the second part of this thesis, p-i-n Ge photodetectors epitaxially grown on Si substrate are fabricated. However, the experimental 3-dB bandwidth is too slow for high speed devices. To overcome the problems, device simulations are carried out for optical generation and photoresponse. To improve the 3-dB bandwidth, RC limit by large junction area and diffusion current limit outside the depletion region should be eliminated. Considering the dark current for low noise application, a thick Ge buffer is needed to prevent the defects generation caused by the misfit at Ge/Si interface. On the other hand, the carrier concentration of intrinsic Ge should also be reduced to increase the depletion width. Summarizing the above mentioned, a Ge on Si n-i-p photodetector with heavily doped p-Ge buffer and lightly doped i-Ge is proposed to improve 3-dB bandwidth and dark current simultaneously.