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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳奕君 | |
dc.contributor.author | Shu-Ming Hsu | en |
dc.contributor.author | 許書銘 | zh_TW |
dc.date.accessioned | 2021-07-10T21:34:37Z | - |
dc.date.available | 2021-07-10T21:34:37Z | - |
dc.date.copyright | 2016-11-02 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-21 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76658 | - |
dc.description.abstract | 本研究成功於玻璃基板上,提升具二氧化鉿背封裝鈍化層之p型氧化亞錫薄膜電晶體的場效載子遷移率,並針對氧化亞錫薄膜受退火溫度、時間和二氧化鉿鈍化層之影響,進行一系列之分析與研究。由於氧化亞錫屬於較不穩定的亞穩態,因此加蓋背封裝鈍化層能有效提升元件的穩定性。
實驗中利用反應式射頻磁控濺鍍系統以金屬錫為靶材在氧氣/(氧氣+氬氣)流量比4.2%的條件下沉積氧化亞錫薄膜,並分別於205°C、225°C、245°C的溫度下進行30秒、1分鐘、2分鐘和3分鐘的短時間退火,結果發現氧化亞錫薄膜具(101)結晶相。當以原子層沉積法沉積二氧化鉿背封裝層後,原先擁有較高開電流值的元件會開始衰退,而原先開電流值較低的元件,則因受原子層沉積製程中溫度與水氣的影響,使其開電流值提高。退火溫度越高,達到最佳載子遷移率所需的時間越短,以205°C退火條件為例,退火時間3分鐘時擁有1.25 cm2V-1s-1的最大載子遷移率,而225°C的元件是於2分鐘時擁有1.16 cm2V-1s-1的最佳表現,至於245°C則是於30秒時,達到0.76 cm2V-1s-1的載子遷移率,相較於未封裝之標準元件(225°C退火30分鐘)的載子遷移率0.40 cm2V-1s-1有明顯改善。而以225°C退火2分鐘的元件來說,當閘極偏壓分別為10 V和-10 V時,經10000秒後臨界電壓偏移量為0.24 V和-0.34 V,相較於未封裝之標準元件所得到之1.01 V和-0.69 V來說,以原子層沉積法沉積之二氧化鉿背封裝層搭配主動層短時間退火可有效改善p型氧化亞錫薄膜電晶體的特性。 | zh_TW |
dc.description.abstract | In this research, the field-effect mobility of on-glass p-type tin monoxide (SnO) thin-film transistors (TFTs) was successfully enhanced by using a short annealing process along with a hafnium oxide (HfO2) back-channel passivation layer. The effects of annealing temperature, annealing time and back-channel passivation on SnO thin films and SnO TFTs were investigated. The as-fabricated SnO thin-films have a metastable phase; therefore, incorporation of a back-channel passivation layer can simultaneously improve the electrical stability of the devices.
The SnO thin films were deposited by reactive rf-sputtering from a metallic tin target at an oxygen / (oxygen + argon) flow ratio of 4.2%. The as-deposited films were then annealed at various temperatures (205°C, 225°C and 245°C) for various durations (30 s, 1 min, 2 min and 3 min). After short annealing processes, SnO thin films with (101) phase were observed. The hafnium oxide passivation layer was deposited by atomic layer deposition (ALD). The SnO TFTs initially exhibiting high on-current showed degraded behavior after the passivation layer was applied, while the performance of SnO TFTs initially exhibiting low on-current was enhanced. The change was caused by the water vapor and elevated temperature during the ALD-passivation process. It was also observed that the higher the annealing temperature, the shorter the annealing duration to achieve the optimal mobility. For instance, the TFT exhibited an optimal mobility of 1.25 cm2V-1s-1 at an annealing temperature of 205°C for 3 min. For films annealed at 225°C and 245°C, the TFT achieved an optimal mobility of 1.16 cm2V-1s-1 and 0.76 cm2V-1s-1 for annealing durations of 2 min and 30 s, respectively. The mobility of unpassivated counterpart annealed at 225°C for 30 min is 0.40 cm2V-1s-1. Under the gate-bias stress of 10 V and -10 V for 10000 s, the threshold voltage shifts for the passivated TFTs are 0.24 V and -0.34 V respectively, while those for the unpassivated TFTs are 1.01 V and -0.69 V, respectively. The results showed the electrical performance of p-type SnO thin-film transistors can be effectively improved by replacing a prolong annealing process with a combination of the short-time annealing and ALD-HfO2 back-channel passivation. | en |
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dc.description.tableofcontents | 口試委員會審定書……………………………….....………………….….…....I
致謝……….........................................................................................II 中文摘要…………………………………..............………………….….……III Abstract…………………………………………...…………………….…..…IV 目錄…………………………………………………...………………….….…VI 圖目錄………………………………………………...………………….….…IX 表目錄…………………………………………........………………….….…XIV 第一章 緒論………………………………………...……………………….….1 1.1 軟性電子發展概況…………………………………..………………….….1 1.2 薄膜電晶體發展背景……………………………..…………………….….1 1.3 研究動機…………………………………………..…………………….….3 1.4 論文架構…………………………………………….………………….…..3 第二章 理論基礎與文獻回顧……………………………………………….….5 2.1 薄膜電晶體簡介……………………………………..………………….….5 2.1.1 薄膜電晶體之結構………………………………...………………….….5 2.1.2 薄膜電晶體之工作原理………………………...…………………….….6 2.1.3 薄膜電晶體之特徵參數………………………...…………………….….7 2.1.4 薄膜電晶體之偏壓穩定性……………….………………………….….10 2.1.5 薄膜電晶體之介電層電性分析……………….…………………….….10 2.2 p型金屬氧化物半導體………………………...…..….……………….….11 2.2.1 p型金屬氧化物半導體之材料…………………...………………….….11 2.2.2 氧化亞錫之材料特性……………………....….…………………….….13 2.3 p型氧化亞錫薄膜電晶體之文獻回顧…………......………………….….18 第三章 實驗方法與步驟……………….....…………….………………….….30 3.1 薄膜沉積方法…………………………………….…………………….….30 3.1.1 反應性射頻磁控濺鍍系統………....……....….…………………….….30 3.1.2 原子層沉積系統………………………………..…………………….….33 3.1.3 電子束蒸鍍系統………………………………..…………………….….34 3.1.4 電漿輔助化學氣相沉積系統……………………..………………….….35 3.2 微影製程之簡介……………………………....….…………………….….36 3.3 蝕刻製程之簡介………………………….....………………………….….38 3.3.1 濕式蝕刻製程………………………………..……………………….….38 3.3.2 乾式蝕刻製程………………………………..……………………….….38 3.4 MIM/MISM電容元件製備流程………………..……………………….….39 3.4.1 MIM元件之製備流程………………………..……………………….….39 3.4.2 MISM元件之製備流程…………...……....………………………….….40 3.5 p型氧化亞錫薄膜電晶體製備流程…………...……………………….….40 3.5.1 基板之前置處理……………………………..……………………….….40 3.5.2 閘極電極之製備………………………………..…………………….….40 3.5.3 閘極介電層之製備……………………………..…………………….….41 3.5.4 主動層之製備…………………………………….………………….…..41 3.5.5 源極/汲極電極之製備…………………………….………………….….41 3.5.6 鈍化層之製備…………………………………..…………………….….41 3.6 量測與分析系統…………………………....………………………….…..42 3.6.1 薄膜穿透率/反射率光譜分析……………………………………….…..42 3.6.2 薄膜X射線繞射分析……………………....…….………………….…...43 3.6.3 元件電容-電壓量測方法…………………….……………………….….45 3.6.4 薄膜電晶體特性量測方法…………………..……………………….….45 3.6.5 薄膜電晶體偏壓穩定性測試方法………..………………………….….46 第四章 結果與討論………………………………………………………….…47 4.1 氧化亞錫薄膜特性分析……………………………………………...……47 4.1.1 退火條件對氧化亞錫薄膜穿透率/反射率光譜之影響…....……..……48 4.1.2 退火時間對氧化亞錫薄膜結晶性之影響………………………………53 4.2 二氧化鉿介電層電容電壓特性分析………………………………...……56 4.3 氧化亞錫薄膜電晶體元件特性分析…………………………………...…57 4.3.1 背通道鈍化層對氧化亞錫薄膜電晶體特性之影響……………………57 4.3.2 退火時間對氧化亞錫薄膜電晶體特性之影響…………………………61 4.3.3 二氧化鉿背封裝鈍化層對氧化亞錫薄膜電晶體穩定性之影響………71 第五章 結論與未來展望…………………………………………………….…74 5.1 結論……………………………………………………………………...…74 5.2 未來展望……………………………………………………………...……76 參考文獻…………………………………………………………...…......……77 | |
dc.language.iso | zh-TW | |
dc.title | P型氧化亞錫薄膜電晶體電性改善之研究 | zh_TW |
dc.title | Enhanced Electrical Performances of P-type Tin Monoxide Thin-Film Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 吳志毅,吳育任,蔡豐羽,陳建彰 | |
dc.subject.keyword | 氧化亞錫,氧化物半導體,p型半導體,薄膜電晶體,鈍化層, | zh_TW |
dc.subject.keyword | tin monoxide,oxide semiconductor,p-type semiconductor,thin-film transistor,passivation layer, | en |
dc.relation.page | 84 | |
dc.identifier.doi | 10.6342/NTU201603317 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2016-08-21 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
顯示於系所單位: | 光電工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
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ntu-105-R03941045-1.pdf 目前未授權公開取用 | 6.2 MB | Adobe PDF |
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