利用電漿增強型原子層沉積技術製作前瞻性高介電材料於金氧半電容元件以及鰭式場效電晶體之研究

Abstract

原子層沉積技術(atomic layer deposition, ALD)可應用在先進半導體製程上，特別是用來成長高介電係數閘極介電層(High-K)，因為它自我限制成膜、一層一層成長以及可低溫成長的特性，使它具有精準原子級尺度的厚度控制、低缺陷、高均勻度和包覆度。本論文研究利用電漿增強型原子層沉積技術(PE-ALD)，來探討不同種類的氧化物在矽基板上作為高介電係數閘極介電層，並將其製作成金屬氧化物半導體(MOS)的電容元件結構，並探討不同電漿氣體處理對氧化物電性的影響，以期高介電係數閘極介電層能應用在鰭狀電晶體上。 論文中第一部分主要討論使用電漿增強型原子層沉積技術摻雜具有不同分佈之氮元素對高介電係數閘極介電層的影響。實驗利用原位原子層摻雜技術 (in situ atomic layer doping)，對上半部或下半部的ZrO2氧化層進行氮化處理 (nitridation)，從介面層(interfacial layer, IL)物理厚度和電性特性得知，對不同部位的結晶ZrO2氧化層進行原位氮化處理，會產生不同的等效氧化層厚度(EOT)和漏電電性表現。第二部分我們使用原子層沉積技術，沉積具不同結構堆疊的高介電係數閘極介電層，來形成金屬氧化物半導體電容元件，並研究其電性和材料物理特性表現。我們從實驗結果發現了差異很大的介電係數特性，藉由原子層沉積技術大幅提升介電層的介電常數特性和降低漏電流表現，來幫助材料尺寸進一步微縮。第三部分利用電漿增強型原子層沉積技術，在鰭式場效奈米電晶體上，整合具前瞻性的閘極介電層，並分析其不同通道長度(gate length)和不同鰭狀寬度(fin width)的電性表現。選擇適合的高介電係數閘極介電層和鰭式場效電晶體製程整合，再從電性量測分析短通道效應和電晶體操作的原理，找出改善鰭式場效電晶體短通道效應和電性表現的方法。第四部分主要探討利用原子層沉積技術並結合氣體電漿，對高介電係數閘極介電層進行電漿處理，並分析氧化層的化學組成和電性特性的變化，深入了解原子層沉積的原理，並改善原子沉積技術製程。

Atomic layer deposition (ALD) is important for semiconductor technology, such as the deposition of high-K dielectrics. In this thesis, high-K dielectrics prepared by plasma enhanced atomic layer deposition (PE-ALD) for metal-oxide-semiconductor (MOS) capacitors and FinFETs were investigated. In the first part, we discussed the impact of nitrogen distribution in ZrO2 gate dielectrics by PE-ALD on MOS capacitors. Amorphous and crystalline ZrO2 gate dielectrics of atomic layer doping of nitrogen by in situ technique were investigated. The capacitance equivalent thickness (CET) and leakage current density (Jg) were effectively suppressed by nitridation. The result reveals that the nitrogen incorporation at the top of crystalline ZrO2 is an effective approach to scale the CET and Jg, as well as to improve the reliability in the MOS devices. In the second part, we investigated the characteristics of cascaded crystalline high-K gate stacks with two structures, TiO2/ZrO2/Al2O3 and Al2O3/ZrO2/TiO2, by plasma atomic enhanced layer deposition (PE-ALD) on Si substrate. The gate stack with different gradient bandgap structure gives rise to the distinct conduction pathways, resulting in significant divergence of CET and Jg. In this part, we demonstrated a way to effectively incorporate the high permittivity and low-bandgap materials, such as TiO2, into high-K gate stacks, to further improve device scaling. In the third part, we demonstrated the application of the high-K dielectrics in FinFET devices by PE-ALD. The ZrO2 and ZrO2/Al2O3 high-K dielectrics on FinFET device with different gate lengths and fin widths were prepared. The improved electrical characteristics in terms of improved subthreshold swing (SS) and reduced drain induced barrier lowering (DIBL) were demonstrated in FinFETs with a narrow fin width. Moreover, the double layer of crystalline ZrO2/Al2O3 buffer layer gate stacks in the FinFETs leads to a further improvement in SS and DIBL. It was found that the ZrO2/Al2O3 high-K gate dielectrics with a narrow fin width is effective to reduce the short channel effects for next-generation FinFETs. The last part is illustrated in the chapter 6, which focuses on the impact of plasma treatment on the electrical properties of HfO2 high-K gate dielectrics by PE-ALD. The plasma treatment was explored to reduce the defect density in the HfO2 high-K dielectric, leading to the reduced leakage current density and improved reliability. The result indicated that the plasma treatment on the high-K gate dielectrics is an effective method to be applied in the plasma process for the future scaling of the high-K gate dielectrics.