請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76450
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 楊佳玲 | |
dc.contributor.author | Chun-Hao Lai | en |
dc.contributor.author | 賴君濠 | zh_TW |
dc.date.accessioned | 2021-07-09T15:52:33Z | - |
dc.date.available | 2021-11-02 | |
dc.date.copyright | 2016-11-02 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-17 | |
dc.identifier.citation | [1] F. Bellard. Qemu, a fast and portable dynamic translator. In Proceedings of the Annual Conference on USENIX Annual Technical Conference, ATEC ’05, pages 41–41, Berkeley, CA, USA, 2005. USENIX Association.
[2] J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp, R. K. Gupta, R. Jhala, and S. Swanson. Nv-heaps: Making persistent objects fast and safe with next-generation, non-volatile memories. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVI, pages 105–118, New York, NY, USA, 2011. ACM. [3] J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee. Better i/o through byte-addressable, persistent memory. In Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles, pages 133–146. ACM, 2009. [4] K. Doshi, E. Giles, and P. Varman. Atomic persistence for scm with a non-intrusive backend controller. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), pages 77–89, March 2016. [5] S. R. Dulloor, S. Kumar, A. Keshavamurthy, P. Lantz, D. Reddy, R. Sankaran, and J. Jackson. System software for persistent memory. In Proceedings of the Ninth European Conference on Computer Systems, EuroSys’14, pages 15:1–15:15, New York, NY, USA, 2014. ACM. [6] O. H. Dushyanth Narayanan. Whole-system persistence with non-volatile memories. In Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2012). ACM, March 2012. [7] E. Giles, K. Doshi, and P. Varman. Bridging the programming gap between persistent and volatile memory using wrap. In Proceedings of the International Conference on Computing Frontiers, pages 30:1–30:10, 2013. [8] D. Hitz, J. Lau, and M. Malcolm. File system design for an nfs file server appliance. In Proceedings of the USENIX Winter 1994 Technical Conference on USENIX Winter 1994 Technical Conference, WTEC’94, pages 19–19, Berkeley, CA, USA, 1994. USENIX Association. [9] Y. Huai. Spin-transfer torque mram (stt-mram): Challenges and prospects. AAPPS Bulletin, 18(6):33–40, 2008. [10] T. Hwang, J. Jung, and Y. Won. Heapo: Heap-based persistent object store. ACM Transactions on Storage (TOS), 11(1):3, 2015. [11] Intel. Instruction set extensions programming reference manual 319433-024 february. https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf, 2016. [12] A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas. Efficient persist barriers for multicores. In Proceedings of the 48th International Symposium on Microarchitecture, MICRO-48, pages 660–671, New York, NY, USA, 2015. ACM. [13] C. Krzysztof and R. Andy. Linux nvm library. https://github.com/pmem/nvml. [14] E. Kültürsay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu. Evaluating stt-ram as an energy-efficient main memory alternative. In Performance Analysis of Systems and Software (ISPASS), 2013 IEEE International Symposium on, pages 256–267. IEEE, 2013. [15] B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable dram alternative. SIGARCH Comput. Archit. News, 37(3):2–13, June 2009. [16] R.-S. Liu, D.-Y. Shen, C.-L. Yang, S.-C. Yu, and C.-Y. M. Wang. Nvm duet: Unified working memory and persistent store architecture. SIGPLAN Not., 49(4):455–470, Feb. 2014. [17] Y. Lu, J. Shu, L. Sun, and O. Mutlu. Loose-ordering consistency for persistent memory. In Computer Design (ICCD), 2014 32nd IEEE International Conference on, pages 216–223. IEEE, 2014. [18] C. Mohan, D. Haderle, B. Lindsay, H. Pirahesh, and P. Schwarz. Aries: A transaction recovery method supporting fine-granularity locking and partial rollbacks using write-ahead logging. ACM Trans. Database Syst., 17(1):94–162, Mar. 1992. [19] Oracle. Nvm direct. https://github.com/oracle/NVM-Direct. [20] A. Patel, F. Afram, S. Chen, and K. Ghose. Marss: A full system simulator for multicore x86 cpus. In Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pages 1050 –1055, june 2011. [21] J. Pedicone, T. Chiacchira, and A. Alvarez. Content addressable memory fifo with and without purging, Apr. 18 2000. US Patent 6,052,757. [22] S. Pelley, P. M. Chen, and T. F. Wenisch. Memory persistency. In Proceeding of the 41st Annual International Symposium on Computer Architecuture, ISCA ’14, pages 265–276, Piscataway, NJ, USA, 2014. IEEE Press. [23] M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture, ISCA’09, pages24–33, New York, NY, USA, 2009. ACM. [24] J. Ren, J. Zhao, S. Khan, J. Choi, Y. Wu, and O. Mutlu. Thynvm: Enabling software-transparent crash consistency in persistent memory systems. In Proceedings of the 48th International Symposium on Microarchitecture, MICRO-48, pages 672–685, New York, NY, USA, 2015. ACM. [25] S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory access scheduling. SIGARCH Comput. Archit. News, 28(2):128–138, May 2000. [26] P. Rosenfeld, E. Cooper-Balis, and B. Jacob. Dramsim2: A cycle accurate memory system simulator. Computer Architecture Letters, 10(1):16–19, 2011. [27] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams. The missing memristor found. nature, 453(7191):80–83, 2008. [28] L. Sun, Y. Lu, and J. Shu. Dp2: Reducing transaction overhead with differential and dual persistency in persistent memory. In Proceedings of the 12th ACM International Conference on Computing Frontiers, CF’15, pages24:1–24:8, NewYork, NY, USA, 2015. ACM. [29] Z. Sun, X. Bi, H. H. Li, W.-F. Wong, Z.-L. Ong, X. Zhu, and W. Wu. Multi retention level stt-ram cache designs with a dynamic refresh scheme. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44, pages 329–338, New York, NY, USA, 2011. ACM. [30] J. Swanson and J. Wickeraad. Apparatus and method for tracking flushes of cache entries in a data processing system, July 8 2003. US Patent 6,591,332. [31] H. Volos, S. Nalli, S. Panneerselvam, V. Varadarajan, P. Saxena, and M. M. Swift. Aerie: Flexible file-system interfaces to storage-class memory. In Proceedings of the Ninth European Conference on Computer Systems, page 14. ACM, 2014. [32] H. Volos, A. J. Tack, and M. M. Swift. Mnemosyne: Light weight persistent memory. SIGPLAN Not., 47(4):91–104, Mar. 2011. [33] X. Wu and A. L. N. Reddy. Scmfs: A file system for storage class memory. In Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis, SC ’11, pages 39:1–39:11, New York, NY, USA, 2011. ACM. [34] J. Xu and S. Swanson. Nova: a log-structured file system for hybrid volatile/non-volatile main memories. In 14th USENIX Conference on File and Storage Technologies (FAST 16), pages 323–338, 2016. [35] M. T. Yourst. Ptlsim: A cycle accurate full system x86-64 microarchitectural simulator. In ISPASS, pages 23–34. IEEE Computer Society, 2007. [36] J. Zhao, S. Li, D. H. Yoon, Y. Xie, and N. P. Jouppi. Kiln: Closing the performance gap between systems with and without persistence support. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, pages 421–432, New York, NY, USA, 2013. ACM. [37] J. Zhao, O. Mutlu, and Y. Xie. Firm: Fair and high-performance memory control for persistent memory systems. In Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-47, pages 153–165, Washington, DC, USA, 2014. IEEE Computer Society. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76450 | - |
dc.description.abstract | 持續記憶體架構是為一融合傳統主記憶體以及儲存單元的的新技術。藉由可接於記憶體匯流排的非揮發隨機存取記憶體 (NVRAM) 可位元組定址能力 (byte-addressability) 以及存儲單元所需要的非揮發特性 (non-volatility),持續記憶體架構將是未來相當重要的新架構。有了持續記憶體架構的出現,將可直接將資料儲存於記憶體之中,而不用再複製到傳統硬碟或者快閃儲存系統。然而為了在記憶體階層保證資料持續性,持續記憶體必須維持資料從中央處理器快取寫到非揮發隨機存取記憶體的寫入順序。直接利用軟體指令來保證寫入順序將會造成許多中央處理器執行的限制而使得整體效能大幅下降。此外,為保證將資料寫入至記憶體的單元性,傳統軟體將會需要額外寫入一些輔助以及日誌資料。因此相關研究提出藉由硬體支援來解決上述效能下降的問題。然而,之前研究所提出的辦法並沒有完全解決此問題,而僅是將效能的負擔傳遞到快取及記憶體階層。因此,我們提出一個高效的硬體方法,提供一個新保證資料持續性的路徑,消除原本硬體架構要維持住寫入順序的負擔以及額外的日誌資料寫入,將整體效能提升至接近於原有沒有保證持續性軟體的效能。 | zh_TW |
dc.description.abstract | Persistent memory is a new technique that merges main memory (DRAM) and storage (disk/flash) into one component. It can be implemented by memory-bus mounted nonvolatile memory (NVRAM), which incorporates the byte-addressability of memory and the non-volatility of storage devices. Persistent memory directly benefits computer system performance by allowing in-memory data to persist immediately without the need for accessing secondary storage, such as flash and disks. However, to ensure data persistence in memory, persistent memory systems need to preserve the ordering of writes from CPU caches toward NVRAM main memory. Directly utilizing the software instructions to ensure the write ordering will push much execution burden on CPUs and result to much performance degradation. Besides, to ensure the atomicity of storing operations to persist data, additional meta-data and logging operations are added into traditional programs without persistence guarantee. And thus, multiple hardware supported solution is proposed. However, previous hardware solutions do not solve the problem at all, which propagates the performance overhead toward cache or memory hierarchy. Therefore, we propose an efficient hardware solution and provide a new persistent path, which frees existing architecture from handling the write ordering, eliminates logging overhead and increases the overall performance near the program without persistence guarantee. | en |
dc.description.provenance | Made available in DSpace on 2021-07-09T15:52:33Z (GMT). No. of bitstreams: 1 ntu-105-R03922024-1.pdf: 4586812 bytes, checksum: fd7631e5e20102d183376d0ed060cee2 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 致謝 i
摘要 ii Abstract iii 1 Introduction 1 2 Background and Motivation 5 2.1 Match Program Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Transaction Atomicity Guarantee . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Program with WAL concept (Persistent Program) . . . . . . . . . . . . . 9 2.4 Software-supported Persistent Program . . . . . . . . . . . . . . . . . . 10 2.4.1 Inefficiency in Software-supported Persistent Program . . . . . . 11 2.5 Related Works to Mitigate Persistence Overhead . . . . . . . . . . . . . . 12 3 Transaction Cache Design 14 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Transaction Cache Example . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Detailed Software and Hardware Modification . . . . . . . . . . . . . . . 18 3.3.1 Transaction Cache Implementation . . . . . . . . . . . . . . . . 18 3.3.2 Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.3 Other Modifications in the Processor . . . . . . . . . . . . . . . 23 3.3.4 Accommodating Multicore Systems . . . . . . . . . . . . . . . . 24 3.3.5 Hardware Overhead . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.6 Detailed Transaction Cache Execution Example . . . . . . . . . . 25 3.4 Detailed Discussions of Multicore Systems . . . . . . . . . . . . . . . . 27 3.4.1 Cache Hierarchy Modification for Mulicore Systems . . . . . . . 30 3.4.2 Hardware Overhead for Multicore Systems . . . . . . . . . . . . 31 4 Experimental Results 32 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3 Sensitivity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 Related Works 40 5.1 NVRAM Access Library . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 NVRAM File System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3 Write Ordering for NVRAM Persistence . . . . . . . . . . . . . . . . . . 41 5.4 Write Atomicity for NVRAM Persistence . . . . . . . . . . . . . . . . . 42 5.5 Scheduling Methods for Stand-alone NVRAM Main Memory System . . 42 6 Conclusion 44 Bibliography 45 | |
dc.language.iso | en | |
dc.title | 高效保證資料持續性之非揮發交易快取 | zh_TW |
dc.title | Nonvolatile Transaction Cache for Efficient Persistence Guarantee | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 呂仁碩,陳坤志,陳依蓉 | |
dc.subject.keyword | 持續記憶體,非揮發記憶體,資料一致性,單元性,耐用性,持續性, | zh_TW |
dc.subject.keyword | Persistent memory,nonvolatile memory,data consistency,atomicity,durability,persistence, | en |
dc.relation.page | 49 | |
dc.identifier.doi | 10.6342/NTU201602526 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2016-08-18 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
dc.date.embargo-lift | 2021-11-02 | - |
顯示於系所單位: | 資訊工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-105-R03922024-1.pdf | 4.48 MB | Adobe PDF | 檢視/開啟 |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。