三維電晶體之自發熱效應及三維積體電路穿矽連通柱之應變/應力

Abstract

本篇論文之目的為對三維電晶體之自發熱效應及三維積體電路穿矽連通柱造成之截止區提出模型並驗證。三維電晶體相比平面電晶體能提供更好的電性表現，然而單位面積功率的提高、材料的低熱導率皆使元件操作溫度升高，而元件溫度升高將導致元件表現衰退及可靠度問題，因此需要有準確的模型及驗證方法，才能監控三維電晶體中的自發熱行為；三維積體電路比起平面系統單晶片有許多優點：更大的頻寬、更短的導線長度、更高的製程選擇靈活度等，然而其所使用之穿矽連通柱於周遭矽晶圓上造成額外的應變將影響元件表現，因此需要有準確的截止區模型作為電路設計的參考。 在自然對流的狀況下，空氣與散熱表面的邊界需考慮一極大的額外熱阻，此熱阻並在晶片面朝上及晶片面朝下時造成元件散熱路徑的不同。為了能準確描述元件的本質自發熱行為，吾人藉由提出之「二階偽等溫面模型」精準的計算後段繞線熱阻，方得以於晶片面朝下及晶片面朝上的條件分別由總熱阻中萃取出鰭式電晶體的本質熱阻。由於鰭式電晶體具備一垂直非對稱結構，在晶片面朝上時，鰭式電晶體有比起晶片面朝下時更大的本質熱阻。藉由電熱模擬軟體，本篇論文指出因矽鍺源/汲極的低熱導係數，在一反向器中，p型元件比起n型元件有更高的操作溫度。反向器中的溫度高低及高溫持續時間可藉由輸出負載電容及元件電流大小來調變。吾人並指出當以交流訊號驅動反向器後，殘存於元件通道中及第一層金屬導線上的溫度比起操作時溫度皆過低，導致量測困難，以至於利用此溫度作為可靠度評估指標可能高估生命期。 本篇論文提出具分佈式熱阻熱容網路之「以積體電路為重點的模擬程式所建立的熱模型」(thermal SPICE)，以解決現有之雙時間常數及單時間常數模型皆無法準確預估交流元件的自發熱效應的問題。在鰭式電晶體中，熱時間常數並非單一數值，而是與輸入頻率成線性相關。邊界散射、合金散射及介面熱阻皆會提高溫度，並皆被本篇論文提出之thermal SPICE納入考量。藉由模組化鰭、金屬導線以及絕緣層，此熱模型具有元件布局及連線的彈性。於美商英特爾(intel)最先進的鰭式電晶體技術文獻指出，其將採用以鈷製成之導線，因鈷導線具有比銅導線長達5倍的電致遷移生命期，然而，當使用本論文提出之thermal SPICE對於環型震盪器進行模擬可發現，因鈷導線的熱傳導係數較低，以所得之鈷導線溫度進行理論投射，其電致遷移生命期在考慮金屬導線溫度上升的情況下對銅導線的優勢將減少至僅剩2.44倍。吾人發現模擬出之溫度可藉由額外擺放於環形震盪器上的第二層連通柱而降低。藉著第二層連通柱達成較低的鈷金屬溫度，可使得鈷導線比起原情況下的銅導線有5.56倍的電致遷移生命期。後段繞線及多鰭鰭式電晶體的熱阻可分別藉由加入額外的熱連通柱及額外的第零層連通柱來降低。 後段繞線完成後才製作之穿矽連通柱在附近的元件中施加額外的應變。本篇論文中於十二吋晶圓上量測28奈米節點元件因穿矽連通柱造成的導通電流變異。在此條件下，穿矽連通柱的應力場受到後段繞線絕緣層的影響，吾人觀察到非對稱之應力場並提出其模型。有別於先前的文獻，由於徑向應力及切線應力絕對值大小並不相同，穿矽連通柱造成的截止區並不對稱。藉由量測結果及三維有限元素分析模擬，吾人提出並驗證了一非對稱截止區模型。並推測因為內建應力大小的不同，n型元件與p型元件被發現有大小相近的截止區。

The purpose of this dissertation is to model the self-heating effect in 3D transistors and the keep-out zone of 3D-IC TSVs. 3D transistors provide better electrostatic as compared to planar transistors. However, the junction temperature increases in 3D transistors due to the increased power density and low thermal conductivity of materials. The high junction temperature degrades device performance and reliability. Accurate self-heating effect modeling can help to monitor the junction temperature for lifetime prediction. 3D-IC has the larger bandwidth, shorter interconnect length, and is more cost effective than 2D SoC. However, the through-silicon vias (TSVs) induce additional strain in nearby Si substrate. The strain field leads to the performance variation in the transistors neighboring to the TSV. Precise keep-out zone (KOZ) modeling is important for the circuit design. With the accurate modeling of the thermal resistance of back-end-of-line (BEOL) by two-step pseudo isothermal plane, the intrinsic thermal resistances of FinFETs are extracted with face-down and face-up configurations. The intrinsic thermal resistance is affected by the direction of heat flow, and it is higher for the face-up configuration than the face-down configuration. The free convection of the air leads to a large thermal resistance. Due to the low thermal conductivity of SiGe S/D, the maximum temperature of pFET is found higher than nFET in an inverter. The output capacitive loading and the current of the inverter can control the maximum temperature and the high temperature duration. With AC input, the temperature in M1 layer and the residual temperature in the channel are found too low as compared to the real device temperature. Using the temperature on metal line as the Tj indicator may overestimate the reliability lifetime. Two tc and one tc models failed to predict accurate AC self-heating results, and a thermal SPICE modeling with distributed Rth-Cth network is proposed in this dissertation. In FinFETs, the thermal time constant of the hotspot is linearly dependent to input frequency instead of a constant. Boundary scattering, alloy scattering, and interfacial thermal resistance raise the temperature and are included in the SPICE. The device layout and interconnect routing flexibilities are achieved by using modularized components of fins, metals, and IMDs. The reported intrinsic electromigration improvement of Co interconnect (5X) could be countervailed (5X→2.44X) by the increasing Tmetal with the projection of Black’s theory. Tj (FinFET) and Tmetal are lowered by placing additional V2 on the power line of a ring oscillator. The predicted EM MTTF of Co interconnect with the lowered Tmetal by V2 insertion is ~5.65X of W/Cu interconnect. The Rth,BEOL and Rth0,FinFET can be reduced by adding thermal via in the BEOL and increasing via0s on the multi-fin FinFETs, respectively. The via-last TSV induced additional strain in nearby devices. The Ion variation is measured using 28nm node devices across 12 inch wafers. The stress field of TSV is affected by the BEOL dielectrics, and an asymmetric stress field is observed and modeled. The absolute value of radial stress does not equal to that of tangential stress and leads to the asymmetric KOZ, different from previously reported. With the help of experiment data and 3D finite element analysis (FEA) simulation, a modified KOZ model with the asymmetric radial and tangential stress field is proposed, fitted, and verified. Different internal stress in device channel leads to comparable KOZ size for nFETs and pFETs.