一個有時間偏移校正之十二位元每秒八億次取樣的時間交錯式連續漸進式類比至數位轉換器

Abstract

在現今很多設備的應用像是無線通訊、智慧電視等等皆需要8位元到12位元每秒取樣幾億次高速取樣以及中高解析度的類比至數位轉換器，放在接收端來處理從傳送器傳來的訊號。 本論文提出了一個有時間偏移校正之十二位元每秒八億次取樣的時間交錯式取樣的連續漸進式類比至數位轉換器，以一個28奈米CMOS製程實現。架構上使用一個六位元的Coarse SAR ADC來輔助四個通道的十二位元Fine SAR ADC的方式，其中為了提高Coarse SAR ADC速度，使用電荷分配的兩階段連續漸進式類比至數位轉換器。 為了要去解決交錯式類比至數位轉換器的通道間時脈偏移不匹配造成線性度不好的問題，提出了一個時脈偏移校正的技巧，使用零交越(zero-crossing)的偵測方式搭配上Coarse ADC和Fine ADC的架構去偵測時脈偏移量，有效降低調整時脈偏移量時所造成的時脈波動(timing fluctuation)，並調整通道間時脈，達成通道間的偏移補償及校正。 本作品的量測結果顯示可操作在每秒八億的轉換及輸入頻率為4億赫茲,SNDR在Fin=20MHz以及Fin=350MHz 分別為59.63dB和49.55dB。功率消耗為4.398 毫瓦。並得到優良的品質因數(FoM)為 16.73 fJ/c.-s。其適合用在高電能效益的無線通訊與乙太網路應用中。

Recently, in many applications, such as wireless communication, smart TV, etc., need 8-bit to 12-bit and sampling rate hundreds MS/s to GS/s medium-to-high resolution analog-to-digital converters, which are placed at the front end of the receiver. This thesis proposed a 12-b 800-MS/s time-interleaved SAR ADC with timing-Skew calibration in 28nm CMOS. The architecture is a 6-bit coarse ADC to assist the 12-bit four fine channel ADC to achieve time-interleaved. In order to increase the conversion speed in coarse ADC, use the two-step SAR ADC with charge sharing technique. Besides, we propose a timing-skew calibration to eliminate the skew effect between the channel. The zero-crossing algorithm is used in our timing-skew calibration and it combined with the subranging architecture so as to reduce timing fluctuation. This time-interleaved SAR ADC achieves SNDR 59.63db at the conversion of 800MS/s with 20MHz input signal and SNDR 49.55db at the conversion of 800MS/s with 350MHz input signal. It consumes 4.398mW and gets a good FoM of 16.73 fJ/conversion-step. It is suitable for energy-efficient wireless communication and an Ethernet network application.