極小半徑矽光子90度波導彎曲結構之設計

Abstract

隨著近年來物聯網、大數據、及雲端計算的蓬勃發展，人們對於數據傳輸的速度需求驟增，如何提升數據中心與其相關的傳輸能力變得格外重要。而擁有較大傳輸容量及較長傳輸距離的矽光子光互聯在數據中心內及數據中心間的連結上有非常大的優勢，因為可以使用成熟的CMOS製程技術來達到低成本與大量生產。而現今的矽光子晶片當中，已有眾多的主動元件與被動元件被研發出來，如何設計出更有效率的波導結構讓晶片上各元件可相互連結會是一個重要議題，此類型設計如交錯（crossings）結構與彎曲（bends）結構，他們會佔整個晶片面積一定分量的比例，而為了節省空間以提升晶片的效能，上述提及之元件尺寸勢必也要微縮，然而彎曲損耗會隨著彎曲半徑縮小成指數大幅上升，這將是未來元件微縮必須克服的難題。本篇論文主要探討超小尺寸波導彎曲結構的設計，雖然本論文尚未實際製作，但為了將本論文之設計可以在製程代工廠實際製作出，因此在考慮元件結構參數時皆以 IMEC 的 iSiPP50G 矽光子元件代工製程技術及規範為根據。為能精確模擬真實元件效能，本論文使用的模擬軟體為Lumerical的三維時域有限差分法求解器，模擬的光源使用波長1.55 μm 的準TE極化之基礎模態。結構設計方面，本研究將45度的路徑等分成5小段曲線，含頭尾共6組分段點處的半徑與其寬度來定義此曲線，再用內插法與對稱的觀念建立路徑平順的90度波導彎曲結構之模型，最後利用粒子群優化演算法計算這6個點的參數來達到最高效能。本論文分別優化等效半徑為2 – 5 μm 之元件設計，整體結果來看本論文設計的效能與相同尺寸之固定半徑的波導彎曲結構相比都可以提升80% 以上，其中等效半徑2 μm 與3 μm 優化後的90度波導彎曲結構元件損耗可達0.011 dB/turn與0.005 dB/turn。製程容忍度方面，等效半徑2 μm 與3 μm 之設計的波導寬度變化在正負10 nm的範圍內，其效能誤差約在10% 左右，此結果對比現有之文獻有相當明顯的突破。

With the development of the internet of things, big data, and cloud computing in recent years, people need increasingly higher data transmission capacity. And to upgrade the transmission capacity of the datacenters becomes more important. Silicon photonic interconnect with large transmission capacity and long transmission distance, has great advantages for the data exchange within a datacenter or between data centers, because the mature CMOS fabrication technology can be used to achieve low cost and mass production. Nowadays, many active and passive components have been developed on the photonics integrated circuits. To connect these components, the design of high-performance silicon waveguide connecting structures, for example, crossings and bends, which connect the components on the photonic integrated circuits, become an important issue. They will account for a certain percentage of the entire real estate on the chip. In order to put more components on the photonic integrated circuits, each component, including the waveguide bends, should be designed more compact. However, for the waveguide bends, the bending loss become exponentially larger as the curvature increases. In this thesis, the designs of small size waveguide bends based on numerical simulations are investigated. Although the designs are not yet fabricated, the CMOS fabrication technology and the mask rule for the iSiPP50G technology provided by IMEC are considered in the thesis so that the design can be manufacturable in the future. To precisely determine the performance of the design, the 3-D FDTD solver developed by Lumerical is used for the simulations in this thesis. The simulation source is quasi-TE fundamental mode and the wavelength is 1.55 μm. To define the structure of the waveguide bend, a 45-degree curved waveguide is divided into 5 smaller curved sections, so that 6 sets of radii of curvature and widths at the joints between smaller curved sections are sufficient to define the entire 45-degree curved waveguide. And then we use interpolation and symmetrical concept to set up the model in to a 90-degree waveguide bend. To achieve a higher performance, we optimize the parameters by using the particle swarm algorithm. Four cases with footprints from 2×2 μm^2 to 5×5 μm^2 are designed and optimized. The results show that the performances of all the designs are improved by at least 80% compared to the conventional waveguide bends with the same radii of curvature. Especially, the loss of the optimally designed 90-degree waveguide bends are 0.011dB/turn and 0.005dB/turn for R _eff= 2 μm and for R_eff = 3 μm , respectively. The performance variation due to the fabrication error of ±10 nanometers is approximately 10% for the designed waveguide bends with R_eff = 2 and 3 μm. The results in this thesis are outstanding compared with previous literature studies.