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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Cheng-Yu Hsieh | en |
| dc.contributor.author | 謝承佑 | zh_TW |
| dc.date.accessioned | 2021-06-17T08:37:03Z | - |
| dc.date.available | 2021-02-22 | |
| dc.date.copyright | 2021-02-22 | |
| dc.date.issued | 2021 | |
| dc.date.submitted | 2021-01-21 | |
| dc.identifier.citation | [1] C. C. Tu, Y. K. Wang, and T. H. Lin, 'A Low-Noise Area-Efficient Chopped VCO-Based CTDSM for Sensor Applications in 40-nm CMOS,' IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2523-2532, Oct. 2017. [2] C. C. Tu, Y. K. Wang, and T. H. Lin, 'A 0.06 mm2 ± 50 mV Range −82dB THD Chopper VCO-Based Sensor Readout Circuit in 40nm CMOS,' 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C84-C85. [3] B. Razavi, Design of Analog CMOS Integrated Circuits, McHraw Hill, 2001. [4] P. G. Drennan and C. C. McAndrew, 'Understanding MOSFET Mismatch for Analog Design,' IEEE Journal of Solid-State Circuits, vol. 38, no. 3, pp. 450-456, Mar. 2003. [5] X. Zou, W. S. Liew, L. Yao, and Y. Lian, 'A 1V 22µW 32-Channel Implantable EEG Recording IC,' 2010 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2010, pp. 126-127. [6] R. Wu, Y. Chae, J. H. Huijsing, and K. A. A. Makinwa, “A 20-b ±40-mV range read-out IC with 50-nV offset and 0.04% gain error for bridge transducers,” IEEE J. Solid–State Circuits, vol. 47, no. 9, pp. 2152–2163, Sep. 2012. [7] H. Jiang, K. A. A. Makinwa, and S. Nihtianov, 'An Energy-Efficient 3.7nV/√Hz Bridge-Readout IC with a Stable Bridge Offset Compensation Scheme,' 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 172-173. [8] G. Singh, R. Wu, Y. Chae, and K. A. A.Makinwa, “A 20bit Continuous-Time ΣΔ Modulator with a Gm-C Integrator, 120dB CMRR and 15 ppm INL,” Proc. IEEE European Solid-State Circuits Conference (ESSCIRC), Bordeaux, 2012, pp. 385–388. [9] N. Maghari and U. K. Moon, 'A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer,' IEEE International Solid-State Circuits Conference, San Francisco, CA, 2011. [10] V. Dhanasekaran et al., 'A Continuous Time Multi-Bit ΔΣ ADC Using Time Domain Quantizer and Feedback Element,' IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 639-650, March 2011. [11] M. Park and M. H. Perrott, 'A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 um CMOS,' IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3344-3358, Dec. 2009. [12] A. Babaie-Fishani and P. Rombouts, 'A Mostly Digital VCO-Based CT-SDM With Third-Order Noise Shaping,' IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2141-2153, Aug. 2017. [13] Collin Wells, 'High-Side Voltage-to-Current (V-I) Converter,' TI Precision Designs: Verified Design, 2013. [14] W. Jiang, V. Hokhikyan, H. Chandrakumar, V. Karkare, and D. Markovic, 'A +-50mV Linear-Input-Range VCO-based Neural-Recording Front-End with Digital Nonlinearity Correction,' IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 173-184, Jan. 2017. [15] A. Jayaraj, M. Danesh, S. T. Chandrasekaran and A. Sanyal, 'Highly Digital Second-Order ΔΣ VCO ADC,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. 2415-2425, July 2019. [16] B. Kim, S. Kundu, S. Ko, and C. H. Kim, 'A VCO-Based ADC Employing a Multi-Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals,' Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, San Jose, CA, 2014, pp. 1-4. [17] P. Prabha et al., 'A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications,' IEEE Journal of Solid-State Circuits, vol. 50, no. 8, pp. 1785-1795, Aug. 2015. [18] J. V. Rethy, H. Danneels, V. D. Smedt, W. Dehaene, and G. E. Gielen, 'Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS,' IEEE Journal of Solid-State Circuits, vol. 48, no. 11, pp. 2618-2627, Nov. 2013. [19] R. Wu, K. A. A. Makinwa, and J.H. Huijsing, “A Chopper Current-Feedback Instrumentation Amplifier with a 1 MHz 1/f Noise Corner and an AC-Coupled Ripple Reduction Loop,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3232 - 3243, Dec. 2009. [20] Q. Fan, F. Sebastiano, J. H. Huijsing, and K. A. A. Makinwa, “A 1.8µW 1µV-Offset Capacitively-Coupled Chopper Instrumentation Amplifier in 65nm CMOS for Wireless Sensor Nodes,” IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1534 - 1543, Jul. 2011. [21] A. Mukherjee et al., 'A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS,' IEEE Journal of Solid-State Circuits, 2020. [22] Pei-Hsuan Huang, 'Design of CMOS Sensor Interface Circuits for EEG and Hall Sensor Applications,' Master thesis, Graduate Institute of Electronics Engineering, National Taiwan University. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74460 | - |
| dc.description.abstract | 本論文著重探討應用於物聯網感測系統之類比數位轉換器電路設計，此電路的主要任務為將振幅小且低頻的信號直接轉換為數位訊號，同時維持訊號的完整度。但由於電路的直流偏移、閃爍雜訊都落在低頻帶的範圍，因此訊號的品質容易受影響，也增加了設計難度。本篇採用環形震盪器作為積分器的連續時間三角積分轉換器，希望在維持低功耗以及低面積同時維持良好的精確度。 本論文對我們所設計的二階連續時間三角積分轉換器做了實作及量測，此電路實作於台積電180奈米製程。為了能夠適應製程演進與物聯網低功耗的需求，我們將供應電壓降為1.2 Ｖ。在低電壓操作的要求之下，我們利用環形震盪器取代類比積分器，以實現感測器電路。這個晶片的設計為將第一級積分過的訊號藉由第二級由環形震盪器所構成的量化器做量化，由於量化器本身具有一階三角積分調變的特性，故整個迴路會有兩階的三角積分調變，且此量化器的數位輸出為一個經動態單元匹配後的訊號，其可以提升數位類比轉換器的線性度，故不需要再加上傳統的動態權重平均電路，而能有較大的頻寬。 此晶片使用1.2 V作為供應電壓，功率消耗為26.2 μW。在160 nAPP的輸入以及2 kHz的頻寬下，可以達到60 dB的信噪比。在品質因素方面達到FoMs = 136.9 dB及FoMw = 10.09 pJ/conv，晶片面積為0.22 mm2。 | zh_TW |
| dc.description.abstract | In this thesis, we will discuss the design of an analog-to-digital converter (ADC) which converts the weak and low-frequency analog signal into digital signal for internet of things (IoT) sensor applications while maintains signal integrity. Since the signal, offset and flicker noise are all in the low-frequency range, the signal is susceptible to these non-idealities and increases the design challenge. The ring oscillator-based integrator is applied to construct continuous-time delta-sigma modulator (CTDSM) to maintain good resolution with the low-power and low-area requirement. This thesis includes the implemented and measured CTDSM designed and fabricated in TSMC 180 nm. The supply voltage is reduced to 1.2V in order to meet the requirement of low power consumption of the IoT. Under the low voltage operation, a ring oscillator is used instead of an analog integrator to implement a sensor circuit. The CTDSM signal would be integrated and enter into the second stage, which is a CCO with phase-to-digital converter as a quantizer. Due to the first-order noise shaping characteristic of the second stage, the whole loop shows second-order noise shaping. The second stage quantize the signal as a digital thermometer code with dynamic element matching (DEM). Comparing with prior art of dynamic weighted averaging (DWA) circuit, this automatic DEM technique can benefit from bigger bandwidth. The core area of the circuit is 0.22 mm2. The SNR is 60 dB (with the bandwidth of 2 kHz) under 160 nAPP input signal. The figure of merits (FoM) FoMs equals to 136.9 dB and FoMw is 10.09 pJ/conv. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T08:37:03Z (GMT). No. of bitstreams: 1 U0001-2001202110573800.pdf: 5879294 bytes, checksum: 1f7fe2488887031901ef4ef0dc9d5c72 (MD5) Previous issue date: 2021 | en |
| dc.description.tableofcontents | Table of Contents 中文審定書 i 英文審定書 iii 摘要 vii Abstract ix List of Figures xiv List of Tables xix Chapter 1 Introduction 1 1.1 Background 1 1.2 Dissertation Overview 2 Chapter 2 Fundamental of Sensor Interface Circuits and Prior Art 3 2.1 Basic Sensor Read-Out Systems 3 2.2 Architectures of IA Circuits 4 2.3 Non-Idealities in Sensor Read-Out Systems 7 2.3.1 Offset Voltage 7 2.3.2 Noise Response 7 2.4 AFE with IA and ADC 9 2.5 Delta-Sigma Modulators 12 2.5.1 Introduction of Delta-Sigma Modulators 12 2.5.2 Models of First-Order Discrete-time DSM 15 2.5.3 Models of Discrete-time Second-order DSM 17 2.5.4 Continuous-Time Delta-Sigma Modulators 18 Chapter 3 Design of Current-Controlled Oscillator and CCO-based Quantizers 20 3.1 Fundamentals of VCO-based Integrators 20 3.2 Current-Controlled Oscillator-based Integrator 22 3.2.1 Introduction to Current-Controlled Oscillators 22 3.2.2 Architecture and Operation of CCO 23 3.2.3 Design of CCO Integrator 25 3.2.4 Principle of the CCO-based Integrator 30 3.3 CCO-based Quantizer 31 3.3.1 Noise-shaped Quantizer 31 3.3.2 FDC CCO-Based Quantizer 31 3.3.3 Transient Respond of FDC CCO-Based Quantizer 33 3.4 Conclusion 37 Chapter 4 Design of a 2nd-order CCO-based CTDSM 38 4.1 Introduction 38 4.2 System Architecture 41 4.3 Building Blocks 45 4.3.1 First Stage CCO (CCO1) 45 4.3.2 Phase Frequency Detector 48 4.3.3 Current Control Circuit 49 4.3.4 Second Stage CCO (CCO2) and FDC Quantizer 51 4.3.5 Feedback Digital-to-Analog Converter (DAC) 55 4.4 Noise Analysis 56 4.5 System Simulation Results 61 Chapter 5 Experimental Result of the 2nd-order CCO-based CTDSM 64 5.1 Die Photo 64 5.2 Measurement Environment Setup 64 5.3 PCB Board 65 5.4 Measurement Result 67 5.4.1 Power Measurement 67 5.4.2 FFT Analyze Diagram 68 5.4.3 Dynamic Range and Linearity 70 5.5 Discussion and Summary 77 Chapter 6 Conclusions and Future Works 79 6.1 Conclusions 79 6.2 Future Works 79 References 81 | |
| dc.language.iso | en | |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 低雜訊 | zh_TW |
| dc.subject | 感測器 | zh_TW |
| dc.subject | 類比前端電路 | zh_TW |
| dc.subject | 環形震盪器 | zh_TW |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | Analog to Digital Converter (ADC) | en |
| dc.subject | Low-Noise | en |
| dc.subject | Sensor | en |
| dc.subject | Analog Front-End (AFE) | en |
| dc.subject | Low-Power | en |
| dc.subject | Ring Oscillator | en |
| dc.title | 基於電流控制震盪器二階連續時間三角積分器設計 | zh_TW |
| dc.title | Design of a Current-Controlled Oscillator-Based 2nd-order Continuous-Time Delta-Sigma Modulator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 109-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),黃柏鈞(Po-Chun Huang),劉深淵(Shen-Iuan Liu) | |
| dc.subject.keyword | 低功率,低雜訊,感測器,類比前端電路,環形震盪器,類比數位轉換器, | zh_TW |
| dc.subject.keyword | Low-Power,Low-Noise,Sensor,Analog Front-End (AFE),Ring Oscillator,Analog to Digital Converter (ADC), | en |
| dc.relation.page | 84 | |
| dc.identifier.doi | 10.6342/NTU202100099 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2021-01-21 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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