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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎 | |
| dc.contributor.author | Yu-Hsiang Chang | en |
| dc.contributor.author | 章宇翔 | zh_TW |
| dc.date.accessioned | 2021-06-17T08:25:58Z | - |
| dc.date.available | 2020-08-16 | |
| dc.date.copyright | 2019-08-16 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-08-12 | |
| dc.identifier.citation | T. H. Li. (2017). A Flexible Hybrid Fault Simulator for Software-Based Self-Test (Unpublished master’s thesis). National Taiwan University, Taipei, Taiwan.
T. H. Lin. (2018). Software-Based Self-Test for Aging Defect Detection (Unpublished master’s thesis). National Taiwan University, Taipei, Taiwan. L. T. Wang, Charles E. Stroud, Nur A. Touba, System-on-Chip Test Architectures: Nanometer Design for Testability. United States: Morgan Kaufmann, 2008, ch.11. P. C. Maxwell, V. Johansen and I. Chiang, 'Functional and Scan Tests: The Effectiveness of I/sub DDQ/ How Many Fault Coverages Do We Need? ,' Proceedings International Test Conference 1992, Baltimore, MD, 1992, pp. 168-177. D. Gizopoulos et al., 'Systematic Software-Based Self-Test for Pipelined Processors,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 11, pp. 1441-1453, Nov. 2008. L. Chen, S. Dey, P. Sanchez, K. Sekar and Y. Chen, 'Embedded Hardware and Software Self-Testing Methodologies for Processor Cores,' Proceedings 37th Design Automation Conference, 2000, pp. 625-630. A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis and Y. Zorian, 'Deterministic Software-Based Self-Testing of Embedded Processor Cores,' Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, Munich, 2001, pp. 92-96. S. Almukhaizim, P. Petrov and A. Orailoglu, 'Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit,' Proceedings 10th Asian Test Symposium, Kyoto, 2001, pp. 319-324. J. Arlat et al., 'Fault Injection for Dependability Validation: A Methodology and Some Applications,' in IEEE Transactions on Software Engineering, vol. 16, no. 2, pp. 166-182, Feb 1990. U. Gunneflo, J. Karlsson and J. Torin, 'Evaluation of Error Detection Schemes Using Fault Injection by Heavy-ion Radiation,' 1989 The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers, Chicago, IL, USA, 1989, pp. 340-347. P. Kenterlis, N. Kranitis, A. Paschalis, D. Gizopoulos and M. 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Pravadelli, 'Efficient Fault Injection in QEMU,' 2015 16th Latin-American Test Symposium (LATS), Puerto Vallarta, 2015, pp. 1-6. K. K. Goswami, 'DEPEND: A Simulation-Based Environment for System Level Dependability Analysis,' in IEEE Transactions on Computers, vol. 46, no. 1, pp. 60-74, Jan 1997. W. C. Lai, A. Krstic and K. T. Cheng, 'Test Program Synthesis for Path Delay Faults in Microprocessor Cores,' Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), Atlantic City, NJ, 2000, pp. 1080-1089. V. Singh, M. Inoue, K. K. Saluja and H. Fujiwara, 'Software-Based Delay Fault Testing of Processor Cores,' 2003 Test Symposium, 2003, pp. 68-71. C. H. P. Wen, L. C. Wang, K. T. Cheng, K. Yang, W. T. Liu and J. J. Chen, 'On a Software-Based Self-Test Methodology and Its Application,' 23rd IEEE VLSI Test Symposium (VTS'05), 2005, pp. 107-113. S. Gurumurthy, R. Vemu, J. A. Abraham and D. G. Saab, 'Automatic Generation of Instructions to Robustly Test Delay Defects in Processors,' 12th IEEE European Test Symposium (ETS'07), Freiburg, 2007, pp. 173-178. Sachin S. Sapatnekar, “What happens when circuits grow old: Aging issues in CMOS design,” 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2013 CíceroNunes, Paulo F.Butzen, André I.Reis, Renato P.Ribas, “BTI, HCI and TDDB aging impact in flip–flops,” in Microelectronics Reliability, vol. 53, issues 9–11, pp. 1355-1359, September–November 2013 Paul BC, Member S, Kang K, Member S, Kufluoglu H, et al. “Negative bias temperature instability: estimation and design for improved reliability of nanoscale circuits,” IEEE Trans Comput Aided Des Integrated Circ Syst pp.743-51, 2007 E. Y. Wu, E. J. Nowak, A. Vayshenker, W. L. Lai, and D. L. Harmon, “CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics,” IBM Journal of Research & Development, 46(2/3), pp. 287–298, March–May 2002. Kaczer B, Degraeve R, Roussel P, Groeseneken G. ”Gate oxide breakdown in FET devices and circuits: from nanoscale physics to system-level reliability,” Microelectronics Reliability, pp. 559–66, 2007. Magnone P, Crupi F, Wils N, Jain R, Tuinhout H, Andricciola P, et al. “Impact of hot carriers on nMOSFET variability in 45- and 65-nm CMOS technologies,” IEEE Trans Electron Dev, pp. 2347–53, 2011 D. Gizopoulos et al., 'Systematic Software-Based Self-Test for Pipelined Processors,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 11, pp. 1441-1453, Nov. 2008. A. Riefert, L. Ciganda, M. Sauer, P. Bernardi, M. S. Reorda and B. Becker, 'An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults,' 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2014, pp. 1-6. A. U. R. Shaheen, F. A. Hussin, N. H. Hamid and N. B. Z. Ali, 'Automatic Generation of Test Instructions for Path Delay Faults Based-On Stuck-At Fault in Processor Cores Using Assignment Decision Diagram,' 2014 5th International Conference on Intelligent and Advanced Systems (ICIAS), Kuala Lumpur, 2014 N. Hage, R. Gulve, M. Fujita and V. Singh, 'On Testing of Superscalar Processors in Functional Mode for Delay Faults,' 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017, pp. 397-402. G. Ayers, A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. (Old University of Utah XUM archieve), 2014, from https://github.com/grantae/mips32r1_xum | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74243 | - |
| dc.description.abstract | 應用軟體自我測試(software-based self-test)提供了非侵入性、功能性以及全速測試的方案，對比於傳統結構性測試，應用軟體自我測試在電路的正常工作模式中，可測試性設計電路將可以被消除，所以並不會有額外面積花費。在應用軟體自我測試中最重要的部分是產生高品質的測試程式，測試程式是測試指令串的集合，處理器執行測試程式來實現自我測試。
在本論文中，我們提出一個基於模擬的測試程式產生方式。目標是偵測出在執行應用程式或測試程式時因為電路老化缺陷而造成的硬體錯誤，我們將模擬因電路老化效應而造成的轉態延遲錯誤(transition delay fault) 以偵測其造成的現象。 | zh_TW |
| dc.description.abstract | The software-based self-test (SBST) provides a non-intrusive, functional and at-speed testing. Compared to conventional structural test, the SBST is applied in normal functional mode of circuit. The design for test (DFT) circuit can be eliminated, so there is no area overhead in SBST. The most important part of SBST is the high quality test program generation. A test program is a set of instruction sequences which can detect the faults. The processor execute the test program to test itself.
In this thesis, we propose a simulation-based test program generation methodology. The purpose is to detect the possible hardware faults caused by aging effect during the execution of applications or test programs. We model the fault behavior as transition delay fault models for aging fault simulation. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T08:25:58Z (GMT). No. of bitstreams: 1 ntu-108-R06943099-1.pdf: 4470759 bytes, checksum: 07b98d49a65348bde67fce306cc15bdb (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES ix Chapter 1 Introduction 1 1.1 Motivation 2 1.1.1 The bottle neck of testing 2 1.1.2 Software-based self-test 3 1.1.3 Challenge of software-based self-test 4 1.1.4 Application of software-based self-test 5 1.2 Previous Work 5 1.2.1 Fault injection approaches 5 1.2.2 Test program generation approaches 6 1.3 Contribution 7 1.4 Organizations of the Thesis 8 Chapter 2 Aging Effect and Delay Fault Testing 9 2.1 Aging Effect 10 2.2 Delay Fault Testing 11 2.3 Transition Delay Fault 12 2.4 Software-Based Delay Fault Testing 14 Chapter 3 Proposed Method for Software-Based Self-Test on Delay Defects 15 3.1 Proposed Methodology 16 3.2 Test Generation 17 3.2.1 Design under test 17 3.2.2 Fault list 18 3.2.3 ATPG constraints 19 3.2.4 ATPG-aided test generation 22 3.3 Find Controlling Sequence 22 3.3.1 Random simulation setup 23 3.3.2 One instruction controlling sequence 24 3.3.3 Multiple instructions controlling sequence 26 3.3.4 Summary 29 3.4 Observation Sequence 29 3.5 Test Template 30 3.5.1 Operand preparation 30 3.5.2 Test template 1 31 3.5.3 Test template 2 33 Chapter 4 Experiment Result 35 4.1 Experiment Setup 36 4.2 NC-Verilog Fault Simulation Result 38 4.2.1 Test program 1 38 4.2.2 Test program 2 39 4.2.3 Test program 1 vs test program 2 40 4.2.4 ATPG vs test program 42 4.2.5 Summary 44 4.3 Hybrid Fault Simulation Result 44 4.4 Full Processor Fault Simulation 46 Chapter 5 Conclusion 48 REFERENCE 50 | |
| dc.language.iso | en | |
| dc.subject | 轉態延遲錯誤 | zh_TW |
| dc.subject | 基於模擬的測試程式產生 | zh_TW |
| dc.subject | 應用軟體自我測試 | zh_TW |
| dc.subject | 積體電路系統測試 | zh_TW |
| dc.subject | Software-Based Self-Test | en |
| dc.subject | Transition Delay Fault | en |
| dc.subject | Simulation-based Test Program Generation | en |
| dc.subject | VLSI System Testing | en |
| dc.title | 基於模擬測試圖樣至程式轉換器應用於軟體自我測試 | zh_TW |
| dc.title | Simulation-Based Test Patterns to Program Converter for Software-Based Self-Test | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李進福,江蕙如,黃炫倫 | |
| dc.subject.keyword | 應用軟體自我測試,轉態延遲錯誤,基於模擬的測試程式產生,積體電路系統測試, | zh_TW |
| dc.subject.keyword | Software-Based Self-Test,Transition Delay Fault,Simulation-based Test Program Generation,VLSI System Testing, | en |
| dc.relation.page | 53 | |
| dc.identifier.doi | 10.6342/NTU201901857 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-08-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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