RISC-V 向量指令集鏈結微架構評估

Abstract

近幾年來，向量架構似乎逐漸死灰復燃。RISC-V 是一設計從微處理器及超級電腦都能適用之嶄新計算機架構，而讓效能可如此擴增的關鍵為其向量指令集。相較於多媒體單指令多資料流指令集架構，RISC-V 向量指令集允許已向量化程式被任何具不同向量長度之微架構所執行。雖然執行一個向量指令可能需要多個處理器週期，但鏈結微架構 (Vector Chaining) 也被隨之提出用來減緩指令發射延遲。 在本論文中，我們在一 RISC-V 處理器模擬器內打造了一克雷 (Cray) 風格之向量微架構。我們不僅評估了各種鏈結微架構情景之效能，也評估了不同處理器資源對鏈結微架構造成的影響。除此之外，我們發現符合特定條件之程式碼在經過適當的程式碼最佳化後，缺乏鏈結微架構之向量處理器仍可達到幾與具鏈結微架構之向量處理器相同的效能。最後，我們整理出了這些可以被程式碼最佳化與不可被最佳化的情景，並對真實的應用程式進行鏈結微架構影響之概略評估。

Reemergence of vector architecture seems to be around the corner in recent years. RISC-V is a brand-new computer architecture designed to scale from low-power microcontrollers to high-performance supercomputers. The key to such a scalable performance is its vector extension. Compared to multimedia SIMD instruction set, RISC-V Vector Extension enables vectorized program could be run in any implementations with different vector lengths. Since a vector instruction may take multiple cycles, Vector Chaining is often implemented to allow the depending vector instruction to start execution as soon as possible. In this thesis, we craft a Cray-style vector microarchitecture by utilizing an in-house cycle-accurate RISC-V CPU simulator. Then, we evaluate the performance tradeoffs between the full chaining and restricted chaining implementations and the impact of chaining across various vector processor configurations. Furthermore, in some scenarios, we find that implementations without chaining could have nearly the same performance as one with chaining via appropriate code optimizations. Finally, we identify those optimizable and unoptimizable scenarios and give an estimated performance evaluation of vector chaining impact on real applications.