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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王暉(Huei Wang) | |
| dc.contributor.author | Ying Chen | en |
| dc.contributor.author | 陳潁 | zh_TW |
| dc.date.accessioned | 2021-06-17T07:37:51Z | - |
| dc.date.available | 2024-03-27 | |
| dc.date.copyright | 2019-03-27 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-03-21 | |
| dc.identifier.citation | [1] Alwyn Wootten, and A. Richard Thompson, “The Atacama large millimeter/submillimeter array,” Proceedings of the IEEE, vol.97, no. 8, pp. 1463-1471, Aug. 2009.
[2] Dixian Zhao, and Patrick Reynaert, CMOS 60-GHz and E-band Power Amplifiers and Transmitters, Switzerland: Springer International Publishing, 2015. [3] Noёl Deferm, and Patrick Reynaert, CMOS Front Ends for Millimeter Wave Wireless Communication System, Switzerland: Springer International Publishing, 2015. [4] Yuan-Hung Hsiao, Zuo-Min Tsai, Hsin-Chiang Liao, Jui-Chi Kao, and Huei Wang, “Millimeter-wave CMOS power amplifiers with high output power and wideband performances,” IEEE Trans. Microwave Theory and Tech., vol. 61, no. 12, pp. 4520-4533, Dec. 2013. [5] Raymond Pengelly, Christian Fager, and Mustafa Özen, “Doherty’s Legacy,” IEEE Microwave Magazine, vol. 17, no. 8, pp. 41-58, Feb. 2016. [6] Jyh-Chyurn Guo, Ching-Shiang Lin, and Yu-Tang Liang, “Low voltage and low power UWB CMOS LNA using current-reused and forward body biasing techniques,” 2017 IEEE MTT-S International Microwave Symposium Digest, Honolulu, HI, USA, Jun. 2017. [7] Mahdi Parvizi, Karim Allidina and, Mourad N. El-Gamal, “A sub-mW, ultra-low-voltage, wideband low-noise amplifier design technique,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, no. 6, pp. 1111-1122, Jun. 2015. [8] Chia-Lin Hsieh, Ming-Hang Wu, Jen-Hao Cheng, Jeng-Han Tsai, and Tian-Wei Huang, “A 0.6-V 336-μW 5-GHz LNA using a low-voltage and gain-enhancement architecture,” 2013 IEEE MTT-S International Microwave Symposium Digest, Seattle, WA, USA, Jun. 2013. [9] Jen-Hao Cheng, Chia-Lin Hsieh, Ming-Hang Wu, Jeng-Han Tsai, and Tian-Wei Huang, “ A 0.33 V 683 μW K-band transformer-based receiver front-end in 65 nm CMOS technology,” IEEE Microwave and Wireless Components Letters, vol.25, no. 3, pp. 184-186, Mar. 2015. [10] Cheng-Ming Chou and Kuang-Wei Cheng, “A sub-2 dB noise-figure 2.4 GHz LNA employing complementary current reuse and transformer coupling,” IEEE International Symposium of Radio Frequency Integrated Technology (RFIT), Taipei, Taiwan, Aug. 2016. [11] Zhiqun Li, Zengqi Wang, Meng Zhang, Liang Chen, Chenjian Wu, and Zhigong Wang, “A 2.4 GHz ultra-low-power current-reuse CG-LNA with active Gm-boosting technique,” IEEE Microwave and Wireless Components Letters, vol.24, no. 5, pp.348-350, May 2014. [12] Mahdi Parvizi, Karim Allidina and Mourad N. El-Gamal, “An ultra-low-power wideband inductorless CMOS LNA with tunable active shunt-feedback,” IEEE Transactions on Microwave Theory and Techniques, vol.64, no. 6, pp.1843-1853, Jun. 2016. [13] Rafaella Fiorelli, Fernando Silveira, and Eduardo Peralias, “Most‒moderate weak-inversion region as the optimum design zone for CMOS 2.4-GHz CS-LNAs,” IEEE Transactions on Microwave Theory and Techniques, vol.62, no. 3, pp.556-566, Mar. 2014. [14] Duy P. Nguyen, Jeffery Curtis, and Anh-Vu Pham, “A Doherty amplifier with modified load modulation scheme based on load-pull data,” IEEE Transactions on Microwave Theory and Techniques, vol. 66, no.1, pp. 227–236, Jan. 2018. [15] Jeffery Curtis, Anh-Vu Pham, Mohan Chirala, Farshid Aryanfar, and Zhouyue Pi, “A Ka-band Doherty power amplifier with 25.1 dBm output power, 38% peak PAE and 27% back-off PAE,” 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Seattle, WA, USA, Jun. 2013. [16] Roberto Quaglia, Vittorio Camarchia, Tao Jiang, Marco Pirola, Simona Donati Guerrieri, and Brian Loran, “A K-band GaAs MMIC Doherty power amplifier for microwave radio with optimized driver,” IEEE Transactions on Microwave Theory and Techniques, vol. 62, no.11, pp. 2518–2525, Nov. 2014. [17] Duy P. Nguyen, Thanh Pham, and Anh-Vu Pham, “A Ka-band asymmetrical stacked-FET MMIC Doherty power amplifier,” 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, USA, Jun. 2017. [18] Duy P. Nguyen, Binh L. Pham, and Anh-Vu Pham, “A compact 29% PAE at 6 dB power back-off E-mode GaAs pHEMT MMIC Doherty power amplifier at Ka-band,” 2017 IEEE MTT-S International Microwave Symposium (IMS), Honolulu, HI, USA, Jun. 2017. [19] Guansheng Lv, Wenhua Chen, and Zhenghe Feng, “A compact and broadband Ka-band asymmetrical GaAs Doherty power amplifier MMIC for 5G communications,” 2018 IEEE MTT-S International Microwave Symposium (IMS), Philadelphia, PA, USA, Jun. 2018. [20] Jeng-Han Tsai, and Tian-Wei Huang, “A 38-46 GHz MMIC Doherty power amplifier using post-distortion linearization,” IEEE Microwave and wireless Components Letters, vol. 17, no.5, pp. 388–390, May 2007. [21] Paramartha Indirayanti, and Patrick Reynaert, “A 32 GHz 20 dBm-PSAT transformer-based Doherty power amplifier for multi-Gb/s 5G applications in 28 nm bulk CMOS,” 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, USA, Jun. 2017. [22] Yen-Chih Chen, Yu-Hsuan Lin, Jung-Lin Lin, and Huei Wang, “A Ka-band transformer-based Doherty power amplifier for multi-Gb/s application in 90-nm CMOS,” IEEE Microwave and wireless Components Letters, vol. 28, no.12, pp. 1134–1136, Nov. 2018. [23] Bumman Kim, Jangheon Kim, Ildu Kim, and Jeonghyeon Cha, “The Doherty power amplifier,” IEEE Microwave Magazine, vol. 7, no. 5, pp. 42-50, Oct. 2006. [24] Jangheon Kim, Jeonghyeon Cha, Ildu Kim, and Bumman Kim, “Optimum operation of asymmetrical-cells-based linear Doherty amplifiers‒‒‒uneven power drive and power matching,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no.5, pp. 1802–1809, May 2005. [25] Theodore S. Rappaport, Shu Sun, Rimma Mayzus, Hang Zhao, Yaniv Azar, Kevin Wang, George N. Wong, Jocelyn K. Schulz, Mathew Samimi, and Felix Gutierrez, “Millimeter wave mobile communications for 5G cellular: it will work!,” IEEE Access, vol. 1, pp. 335–349, May 2013. [26] T. Lüthi, D. Rabanus, U. U. Graf, C. Granet, and A. Murk, “A new multibeam receiver for KOSMA with scalable fully reflective focal plane array optics,” 16th International Symposium on Space Terahertz Technology, Goteborg, Sweden, May 2005. [27] Eric Bryerton, Matthew Morgan, and Marian Pospieszalski, “Ultra low noise cryogenic amplifiers for radio astronomy,” 2013 IEEE Radio and Wireless Symposium (RWS), Austin, TX, USA, Jan. 2013. [28] Rosario M. Incandela, Lin Song, Harald Homulle, Edoardo Charbon, Andrei Vladimirescu, and Fabio Sebastiano, “Characterization and compact modeling of nanometer CMOS transistors at deep-cryogenic temperatures,” IEEE Journal of the Electron Devices Society, vol. 6, pp. 996–1006, Apr. 2018. [29] Hiroaki Namba, Takasuke Hashimoto, and Masayuki Furumiya, “On-chip vertically coiled solenoid inductors and transformers for RF SoC using 90nm CMOS interconnect technology,” 2011 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Baltimore, MD, USA, Jun. 2011. [30] Yu-Ting Chou, Chau-Ching Chiong, and Huei Wang, “A Q-band LNA with 55.7% bandwidth for radio astronomy applications in 0.15-μm GaAs pHEMT process,” IEEE International Symposium of Radio Frequency Integrated Technology (RFIT), Taipei, Taiwan, Aug. 2016. [31] Hector Solar Ruiz and Roc Berenguer Pérez, Linear CMOS RF Power Amplifiers, 1st ed., New York, USA: Springer US, 2014. [32] Wei-Cheng Huang, “Design of differential LNA for radio astronomy receiver and high-efficiency K-band CMOS-based power amplifier with inductance-based neutralization for 5G communication,” Master dissertation, National Taiwan University, Oct. 2018. [33] Yang Chang, Bo-Ze Lu, Yunshan Wang, and Huei Wang, “A Ka-Band stacked power amplifier with 24.8-dBm output power and 24.3% PAE in 65-nm CMOS technology,” 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, USA, Jun. 2019. [34] Yen-Chih Chen, “Design of the broadband LNA and Ka-band PA,” Master dissertation, National Taiwan University, Jan. 2018. [35] “0.15-μm InGaAs pHEMT power device model handbook,” WIN Semiconductor Inc., 2010. [36] 陳炳佑撰，三、五族電晶體模型與Ka頻段放大器設計，國立台灣大學電機工程研究所碩士論文，2002年。 [37] 黃品澄撰，寬頻微波功率放大器之研究，國立台灣大學電信工程學研究所博士論文，2011年。 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/73489 | - |
| dc.description.abstract | 本論文包含兩部分。第一部分是一個針對下個世代的無線電天文接收機之需求所設計的C波段(C-band)極低功耗(ultra-low-power)低雜訊放大器。第二部分是一個支持高頻段第五代無線通訊系統的Ka波段(Ka-band)多爾蒂功率放大器(Doherty power amplifier)。
第一部分的論文呈現了一個使用90奈米金氧半場效電晶體製程設計的C-band極低功耗低雜訊放大器，這個寬頻低雜訊放大器支持ALMA頻段中4-6 GHz的頻段。為了因應嚴格的功率限制，我們提出了一個合適的偏壓選擇方法，同時，我們利用串級的共源極放大器和四個元件組成的阻抗匹配網路來增加放大器頻寬。此放大器在消耗963微瓦之下，在42.4%的分頻寬比內提供平均17.5 dB的小訊號增益以及平均3.1 dB的雜訊指數，在目前已發表的S波段(S-band)以及C波段低功耗低雜訊放大器中具有競爭力。 第二部分的論文展示了一個使用0.1微米砷化鎵假型高速場效電晶體(pHEMT)製程設計的Ka波段多爾蒂(Doherty)功率放大器。為了支持第五代無線通訊系統，這個功率放大器的操作頻率鎖定在37-40 GHz來提供較佳的頻寬和位元速率。我們採用對稱的多爾蒂放大器架構以及二級共源極放大器來維持良好的增益和功率退回時的效率，再者，我們也利用電感與電容共振的方法以及分佈式阻抗轉換器來縮小功率結合網絡所佔據的晶片面積。量測結果顯示此放大器在39 GHz到41 GHz寬中，除了提供23 dBm的飽和輸出功率(Psat)和27-29%的峰值功率附加效率(PAE) ，也在6 dB功率退回處提供20-21%的功率附加效率。在目前已發表的Ka波段砷化鎵多爾蒂功率放大器中，這個作品在40 GHz左右提供最好的6-dB功率退回功率附加效率。 | zh_TW |
| dc.description.abstract | This thesis consists of two parts. The first part presents a C-band ultra-low-power low noise amplifier for next-generation radio astronomical receivers. The other describes a Ka-band Doherty PA supporting the upper-frequency band of fifth-generation wireless systems.
The first part of the thesis presents a C-band ultra-low-power LNA fabricated in TSMC 90-nm CMOS technology. This wideband LNA is targeted on 4-6 GHz, which is a part of IF band in ALMA bands. Due to restricted dc power consumption, a methodology of selecting a proper bias is proposed. Meanwhile, cascaded common-source amplifiers and four-element L-matching network enhance the bandwidth of this work. While consuming only 963 μW, this work demonstrates a 42.6% fractional bandwidth with an average gain of 17.5 dB and an average noise figure of 3.1 dB. To the author’s knowledge, this LNA shows competitiveness among published S-band and C-band low-power LNAs. The other part of the thesis demonstrates a Ka-band Doherty PA fabricated in WIN’s 0.1-μm D-mode GaAs pHEMT process. Supporting 5G wireless systems, the operating frequencies of this work is targeted at 37-40 GHz to provide broader bandwidth and higher data rate. To achieve good gain and backed-off efficiency, a symmetric Doherty configuration and two-stage cell amplifiers are chosen in the design. Moreover, the LC-resonance method and distributed impedance transformer help to reduce the area of the power-combining network. The measured results of this work show a peak PAE of 27-29% and 6-dB backed-off PAE of 20-21% from 39 to 41 GHz while providing a Psat of 23 dBm. To the author’s knowledge, this work exhibits the best 6-dB backed-off efficiency at frequencies around 40 GHz among published Ka-band GaAs Doherty PA. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T07:37:51Z (GMT). No. of bitstreams: 1 ntu-108-R05942092-1.pdf: 12457625 bytes, checksum: ee2d1f4d5883a569682d396b9b5ddbfe (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv CONTENTS vi LIST OF FIGURES viii LIST OF TABLES xv Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.1.1 Next-Generation Radio Astronomical Applications 1 1.1.2 Fifth Generation of Cellular Mobile Communications 2 1.2 Literature Survey 3 1.2.1 Ultra-low-power Low Noise Amplifier in CMOS Technologies 3 1.2.2 Millimeter-wave Doherty Power Amplifier 5 1.3 Contributions 8 1.3.1 C-band CMOS LNA for Future Radio Astronomical Applications 8 1.3.2 Ka-band GaAs pHEMT Doherty PA for 5G Wireless Systems 8 1.4 Thesis Organization 9 Chapter 2 Design of C-Band Ultra-Low-Power Low Noise Amplifier in 90-nm CMOS Technology 10 2.1 Introduction 10 2.2 Circuit Design 13 2.2.1 RFIC Process Characteristic 13 2.2.2 Sub-mW Biasing Method and Device Selection 15 2.2.3 3D-Solenoid Inductors 22 2.2.4 Bandwidth Enhancement Techniques 24 2.2.5 Circuit Schematic and Post-Layout Simulations 28 2.3 Experimental Results 33 2.4 Summary 36 Chapter 3 Design of Ka-Band Doherty Power Amplifier in 0.1-μm D-mode GaAs pHEMT Process 38 3.1 Introduction 38 3.2 Circuit Design 42 3.2.1 MMIC Process Characteristics 42 3.2.2 Circuit Topology 43 3.2.3 Quadrature Power Splitters 44 3.2.4 The Design of Cell Amplifiers 48 3.2.5 Power-combining Network and Load Modulation 64 3.2.6 Circuit Schematic and Post-Layout Simulations 68 3.3 Experimental Results 75 3.3.1 Design of Off-chip Bypass Circuits 76 3.3.2 Measurement of Small-Signal and Large-Signal Performances 79 3.3.3 Measurement of Digital Modulation 82 3.4 Discussion 86 3.5 Summary 107 Chapter 4 Conclusion 109 REFERENCE 110 LIST OF FIGURES Fig. 2.1. Mechanical layout of a 9-pixel array receiver cartridge [26]. 11 Fig. 2.2. The maximum stable gain/maximum available gain (MSG/MAG) of an RF transistor under Class A operation. (Size of the device: 1 μm × 2 fingers) 13 Fig. 2.3. The simulated MSG and NFmin versus Vg of a CS device at 5 GHz. 14 Fig. 2.4. Bias points of a CS device under constant 500-μW PDC. 15 Fig. 2.5. The simulated MSG and NFmin versus Vg under constant 500-μW PDC. 16 Fig. 2.6. MSG and NFmin versus Vg of CS devices under 500-μW PDC. 17 Fig. 2.7. Noise circles under 500-μW PDC. (Size of the device: 1 μm × 30 fingers) 18 Fig. 2.8. Noise circles under 500-μW PDC. (Size of the device: 2 μm × 30 fingers) 19 Fig. 2.9. Noise circles under 500-μW PDC. (Size of the device: 3 μm × 30 fingers) 19 Fig. 2.10. The design flow of device selection. 20 Fig. 2.11. Simulated gain and input return loss of different transistors after applying input matching network. 21 Fig. 2.12. Simulated noise figure of different transistors after applying input matching network. 21 Fig. 2.13. Physical layout of (a) the spiral inductor (b) the 3D-solenoid inductor. 22 Fig. 2.14. The simulated results of the spiral inductor and the 3D-solenoid inductor. 23 Fig. 2.15. Four-element L-matching network with internal LC tanks. 25 Fig. 2.16. Simulated input return loss of the proposed LNA adopting conventional L-matching network and four-element L-matching network. 25 Fig. 2.17. Simulated (a) Zs and (b) noise figure of the proposed LNA adopting conventional L-matching network and four-element L-matching network. 27 Fig. 2.18. Simulated gain and noise figure of the first-stage amplifier and second-stage amplifier. 27 Fig. 2.19. Complete schematic of the ultra-low-power CMOS LNA. 28 Fig. 2.20. Simulated S-parameters of the proposed LNA. 29 Fig. 2.21. Simulated noise figure of the proposed LNA. 30 Fig. 2.22. Simulated stability factor (K) of the proposed LNA. 31 Fig. 2.23. The simulation of inter-stage stability. 31 Fig. 2.24. Chip layout of the proposed LNA. 32 Fig. 2.25. Chip photograph of the proposed ultra-low-power LNA. 33 Fig. 2.26. Simulated and measured S-parameters of the ultra-low-power LNA. 34 Fig. 2.27. Simulated and measured noise figure of the ultra-low-power LNA. 35 Fig. 2.28. Simulated and measured gain and output power of the ultra-low-power LNA at 5 GHz. (Bias: Vg = 0.40 V, Vd = 0.28 V) 35 Fig. 2.29. Two-tone simulation and measurement of the ultra-low-power LNA. 36 Fig. 3.1. Block diagram of a conventional Doherty PA. 39 Fig. 3.2. Operational diagram of the Doherty PA in (a) low-power region and (b) high-power region. 40 Fig. 3.3. Block diagram of the proposed Ka-band Doherty PA. 43 Fig. 3.4. (a) The physical structure and (b) the frequency response of Wilkinson power divider with a delay line. 45 Fig. 3.5. (a) The physical structure and (b) the frequency response of branchline coupler. 45 Fig. 3.6. (a) The illustration and (b) the frequency response of the Lange coupler. 46 Fig. 3.7. Simulated (a) gain imbalance and (b) phase difference between port 2 and port 3 of the three quadrature power splitters. 47 Fig. 3.8. Block diagram of the employed cell amplifier. 48 Fig. 3.9. Simulated MaxGain of the power-stage transistors. 49 Fig. 3.10. Simulated stability factor of the power-stage transistors. 49 Fig. 3.11. Employed bias network for instable transistors of (a) 4 fingers × 50 μm, 8 fingers × 25 μm and (b) 2 fingers × 100 μm. 50 Fig. 3.12. Simulated MaxGain and stability factor of the power-stage transistors after adding proposed bias network. (Bias: Vg = -0.8 V, Vd = 4 V) 51 Fig. 3.13. Load-pull simulation of 2 fingers × 100 μm device at 38 GHz. 52 Fig. 3.14. Load-pull simulation of 4 fingers × 50 μm device at 38 GHz. 52 Fig. 3.15. Load-pull simulation of 8 fingers × 25 μm device at 38 GHz. 53 Fig. 3.16. Simulated large-signal performances of the 2 fingers × 100 μm device. 54 Fig. 3.17. Simulated MaxGain and stability factor of the driver-stage transistors after adding proposed bias network. (Bias: Vg = -0.7 V, Vd = 4 V) 55 Fig. 3.18. Load-pull simulation of 2 fingers × 50 μm device at 38 GHz. 56 Fig. 3.19. Load-pull simulation of 4 fingers × 25 μm device at 38 GHz. 56 Fig. 3.20. Simulated large-signal performances of the 2 fingers × 50 μm device. 57 Fig. 3.21. LC-resonance method: (a) Cancellation of Cpar and (b) Zopt before and after adding an inductive short stub to the drain of the power-stage transistor. 58 Fig. 3.22. Load-pull simulation of the 2 fingers × 100 μm device after adding an inductive short stub to its drain. (Bias: Vg = -0.8 V, Vd = 4 V) 59 Fig. 3.23. Simulated (a) output resistance and (b) output reactance of the Class-C power-stage transistor. (Bias: Vg = -1.2 V, Vd = 4 V) 59 Fig. 3.24. Complete schematic of the main amplifier. 60 Fig. 3.25. Simulated S-parameters of the main amplifier. 61 Fig. 3.26. Simulated large signal performances of the main amplifier at 38 GHz. 61 Fig. 3.27. Block diagram of the auxiliary amplifier. 62 Fig. 3.28. Simulated (a) output resistance and (b) output reactance of the auxiliary amplifier under different Vg2. (Vg1 = -1.0 V, Vd = 4 V for all simulation) 63 Fig. 3.29. Simulated gain and output power of the auxiliary amplifier under different Vg2. (Vg1 = -1.0 V, Vd = 4 V for all simulation) 63 Fig. 3.30. Power-stage amplifier loaded with different impedances. 64 Fig. 3.31. Simulated large signal performances at 38 GHz when the power-stage amplifier is loaded with different impedances. 65 Fig. 3.32. Adopted power-combining network of this work. 66 Fig. 3.33. Simulated load impedances of the main amplifier and auxiliary amplifier versus power back off of the Doherty PA. 66 Fig. 3.34. Distributed impedance transformer. 67 Fig. 3.35. Simulated (a) phase delay and (b) loss of λ/4 impedance transformer and distributed impedance transformer. 67 Fig. 3.36. Complete schematic of the millimeter-wave Doherty PA. 69 Fig. 3.37. Simulated S-parameters of the proposed Doherty PA. 70 Fig. 3.38. Simulated stability factor of the proposed Doherty PA. 71 Fig. 3.39. Simulated large signal performances of the proposed Doherty PA. 71 Fig. 3.40. Simulated AM-AM distortion of the proposed Doherty PA. 72 Fig. 3.41. Simulated AM-PM distortion of the proposed Doherty PA. 72 Fig. 3.42. Simulated gain and PAE of this work under different bias. 73 Fig. 3.43. Chip layout of the proposed Doherty PA. 74 Fig. 3.44. Micrograph of the proposed Doherty PA. 75 Fig. 3.45. Schematic used for checking the stability of (a) driver-stage and (b) power-stage transistors. 77 Fig. 3.46. Complete schematic of the designed off-chip bypass circuit. 77 Fig. 3.47. Simulated stability factor of the driver-stage transistor at low frequencies. 78 Fig. 3.48. Simulated stability factor of the power-stage transistor at low frequencies. 78 Fig. 3.49. Simulated and measured S-parameters of the Doherty PA. 79 Fig. 3.50. Simulated and measured large signal performances of this work at 40 GHz. 80 Fig. 3.51. Measured large signal performances of the proposed Doherty PA. 81 Fig. 3.52. Measured large signal performances of the Doherty PA versus frequency. 81 Fig. 3.53. Measured EVM and PAE versus average output power of this work at 40 GHz. (Digital modulation: 16 QAM) 83 Fig. 3.54. Measured EVM and PAE versus average output power of this work at 40 GHz. (Digital modulation: 64 QAM) 83 Fig. 3.55. Measured EVM versus average output power of this work at 37-40 GHz. (Digital modulation: 64 QAM 800 Mbp/s) 84 Fig. 3.56. Comparison between S-parameters generated through WIN’s nonlinear model and measured S-parameters provided by WIN. (Device: 2 fingers × 50 μm) 86 Fig. 3.57. Comparison between S-parameters generated through WIN’s nonlinear model and measured S-parameters provided by WIN. (Device: 2 fingers × 50 μm) 87 Fig. 3.58. Comparison between S-parameters generated through WIN’s nonlinear model and measured S-parameters provided by WIN. (Device: 2 fingers × 100 μm) 88 Fig. 3.59. Comparison between S-parameters generated through WIN’s nonlinear model and measured S-parameters provided by WIN. (Device: 2 fingers × 100 μm) 89 Fig. 3.60. Comparison between Gm generated through WIN’s nonlinear model and measured Gm provided by WIN. (Device: 2 fingers × 50 μm) 90 Fig. 3.61. Comparison between DCIV curves generated through WIN’s nonlinear model and measured DCIV data provided by WIN. (Device: 2 fingers × 50 μm) 90 Fig. 3.62. Comparison between Gm generated through WIN’s nonlinear model and measured Gm provided by WIN. (Device: 2 fingers × 100 μm) 91 Fig. 3.63. Comparison between DCIV curves generated through WIN’s nonlinear model and measured DCIV data provided by WIN. (Device: 2 fingers × 100 μm) 91 Fig. 3.64. Small signal model provided by WIN [34]. 92 Fig. 3.65. Comparison between S-parameters generated through new linear model and measured S-parameters provided by WIN. (Device: 2 fingers × 50 μm) 94 Fig. 3.66. Comparison between S-parameters generated through new linear model and measured S-parameters provided by WIN. (Device: 2 fingers × 50 μm) 95 Fig. 3.67. Comparison between S-parameters generated through new linear model and measured S-parameters provided by WIN. (Device: 2 fingers × 100 μm) 96 Fig. 3.68. Comparison between S-parameters generated through new linear model and measured S-parameters provided by WIN. (Device: 2 fingers × 100 μm) 97 Fig. 3.69. Measured rch of (a) 2 fingers × 50 μm device and (b) 2 fingers × 100 μm device based on the measured data provided by WIN. 99 Fig. 3.70. Comparison between Gm generated through Angelov model and measured Gm provided by WIN. 99 Fig. 3.71. Comparison between channel current curve generated through Angelov model and measured channel current curve provided by WIN. (Device: 2 fingers × 50 μm) 100 Fig. 3.72. Comparison between channel current curve generated through Angelov model and measured channel current curve provided by WIN. (Device: 2 fingers × 100 μm) 100 Fig. 3.73. Comparison between DCIV curves generated through Angelov model and measured DCIV data provided by WIN. (Device: 2 fingers × 50 μm) 101 Fig. 3.74. Comparison between DCIV curves generated through Angelov model and measured DCIV data provided by WIN. (Device: 2 fingers × 100 μm) 101 Fig. 3.75. Comparison between S-parameters simulated through Angelov model and measured S-parameters. 106 Fig. 3.76. Comparison between large signal performances simulated through Angelov model and measured large signal performances at 40 GHz. 107 LIST OF TABLES Table 1.1 Performance summary of the published low-power CMOS LNAs. 4 Table 1.2 Performance summary of the published Ka-band Doherty PAs. 7 Table 2.1 Specifications of the ultra-low-power CMOS LNA. 12 Table 2.2 Best bias points for different transistors under 500-μW PDC. 17 Table 2.3 The parameters of the inductors in 90-nm CMOS technology. 24 Table 2.4 The bias condition for each stage of the ultra-low-power CMOS LNA. 29 Table 2.5 Performance summary of the published ultra-low-power CMOS LNAs. 37 Table 3.1 The design goals of the proposed Ka-band Doherty PA. 41 Table 3.2 Employed double-metal transmission lines for quadrature power splitters. 45 Table 3.3 The parameters of the employed Lange coupler. 46 Table 3.4 Summary of the three quadrature power splitters. 47 Table 3.5 Detailed values of the employed bias network for power-stage transistors. 51 Table 3.6 Summary of load-pull simulation for power-stage transistors. 53 Table 3.7 Detailed values of the employed bias network for driver-stage transistors. 55 Table 3.8 Summary of load-pull simulation for driver-stage transistors. 57 Table 3.9 The simulated dc condition of the Doherty PA using large signal model. 68 Table 3.10 The measured dc condition of each stage of the Doherty PA. 79 Table 3.11 Parameters in the small signal model. (2 fingers × 50 μm) 93 Table 3.12 Parameters in the small signal model. (2 fingers × 100 μm) 93 Table 3.13 The value of the parameters in the Angelov model. (2 fingers × 50 μm) 102 Table 3.14 The value of the parameters in the Angelov model. (2 fingers × 100 μm) 104 Table 3.15 Performance summary of the published Ka-band Doherty PAs. 108 | |
| dc.language.iso | en | |
| dc.subject | 微波單晶積體電路 | zh_TW |
| dc.subject | 多爾蒂功率放大器 | zh_TW |
| dc.subject | 低功耗元件 | zh_TW |
| dc.subject | 低雜訊放大器 | zh_TW |
| dc.subject | low noise amplifier | en |
| dc.subject | low-power device | en |
| dc.subject | Doherty power amplifier | en |
| dc.subject | monolithic microwave integrated circuit | en |
| dc.title | 微波低功耗低雜訊放大器與毫米波多爾蒂功率放大器的設計 | zh_TW |
| dc.title | Design of Microwave Ultra-Low-Power Low Noise Amplifier and Millimeter-wave Doherty Power Amplifier | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 章朝盛(Chau-Ching Chiong),蔡作敏(Zuo-Min Tsai),蔡政翰(Jeng-Han Tsai),張鴻埜(Hong-Yeh Chang) | |
| dc.subject.keyword | 低雜訊放大器,低功耗元件,多爾蒂功率放大器,微波單晶積體電路, | zh_TW |
| dc.subject.keyword | low noise amplifier,low-power device,Doherty power amplifier,monolithic microwave integrated circuit, | en |
| dc.relation.page | 115 | |
| dc.identifier.doi | 10.6342/NTU201900660 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-03-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-108-1.pdf 未授權公開取用 | 12.17 MB | Adobe PDF |
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