請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/73033完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
| dc.contributor.author | Chieh-Fang Cheng | en |
| dc.contributor.author | 鄭捷方 | zh_TW |
| dc.date.accessioned | 2021-06-17T07:14:41Z | - |
| dc.date.available | 2020-07-30 | |
| dc.date.copyright | 2019-07-30 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-07-16 | |
| dc.identifier.citation | [1] R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and A. Teman, “An 800-MHz Mixed-VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications,” IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 2136-2148, May 2018.
[2] R. Giterman, A. Fish, A. Burg and A. Teman, “A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 4, pp. 1245-1256, Apr. 2018. [3] Y. D. Tan and J. G. Hwu, “2-State Current Characteristics of MOSCAP with Ultrathin Oxide and Metal Gate,” ECS Solid State Lett., vol. 4, no. 12, pp. N23-N25, Nov. 2015. [4] K. H. Tseng, C. S. Liao and J. G. Hwu, 'Enhancement of Transient Two-States Characteristics in Metal-Insulator-Semiconductor Structure by Thinning Metal Thickness,' IEEE Transactions on Nanotechnology, vol. 16, no. 6, pp. 1011-1015, Nov. 2017. [5] K. H. Tseng, “Two-State Current Behavior in MIS Tunnel Diode with Ultra-thin Surrounding Gate Metal Electrode,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ. Taipei, Taiwan, R.O.C., Jul. 2016. [6] N. Yang, W. K. Henson, J. R. Hauser and J. J. Wortman, “Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices,” IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1464-1471, Jul. 1999. [7] Wen-Chin Lee and Chenming Hu, “Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling,” IEEE Transactions on Electron Devices, vol. 48, no. 7, pp. 1366-1373, Jul. 2001. [8] C. W. Lee, “A comprehensive Quantum-Mechanical Model for C-V and I-V Characteristics in Ultrathin MOS Structure and Experimental Verification,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ. Taipei, Taiwan, R.O.C., Jan. 2013. [9] S.M. Sze, and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. New York: Wily, 2006, ch.3, sec. 3.3.6 and ch.8, sec. 8.3.2. [10] C. S. Liao and J. G. Hwu, 'Subthreshold Swing Reduction by Double Exponential Control Mechanism in an MOS Gated-MIS Tunnel Transistor,' IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 2061-2065, Jun. 2015. [11] F. Li, S. P. Mudanai, Y. Y. Fan, L. F. Register, and S. K. Banerjee, “Physically Based Quantum–Mechanical Compact Model of MOS Devices Substrate-Injected Tunneling Current Through Ultrathin (EOT ∼ 1 nm) SiO2 and High-κ Gate Stacks” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1096-1106, May 2006. [12] Y. P. Lin, and J. G. Hwu, “Oxide-Thickness-Dependent Suboxide Width and Its Effect on Inversion Tunneling Current,” J. Electrochem. Soc., vol. 151, no. 12, pp. G853-G857, Oct. 2004. [13] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, New York: Wiley-Interscience, pp. 74, 1981. [14] K. J. Yang and C. Hu, “MOS capacitance measurements for high-leakage thin dielectrics,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1500-1501, Jul. 1999. [15] K. Yang, Y. C. King, and C. Hu, “Quantum effect in Oxide Thickness Determination from Capacitance Measurement,” Symp. VLSI Tech. Dig., pp. 77-78, Jun. 1999. [16] T. Y. Chen, “Process Development and Characterization of MOS capacitor with Ultra-thin Oxide,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ. Taipei, Taiwan, R.O.C., Jun. 2011. [17] Berkeley Device Group: www-device.eecs.berkeley.edu/qmcv/. [18] P. F. Schmidt and W. Michel, “Anodic Formation of Oxide Films on Silicon,” J. Electrochem. Soc., vol. 104, pp. 230-236, 1957. [19] Gong, D., Grimes, C., Varghese, O., Hu, W., Singh, R., Chen, Z., & Dickey, E. (2001). Titanium oxide nanotube arrays prepared by anodic oxidation. Journal of Materials Research, 16(12), 3331-3334. [20] Chieh-Chih Ting, Yen-Hao Shih and Jenn-Gwo Hwu, “Ultralow leakage characteristics of ultrathin gate oxides (~3 nm) prepared by anodization followed by high-temperature annealing,” IEEE Transactions on Electron Devices, vol. 49, no. 1, pp. 179-181, Jan. 2002. [21] M. J. Jeng, “Application of Anodic Oxidation and Rapid Thermal Treatment on Thin Gate Oxides and Radiation-Hard CMOS Circuit Design” Ph. D. dissertation, Dept. Elect. Eng. Nat. Taiwan Univ. Taipei, Taiwan, R. O. C., 1996. [22] S.K. Ghandhi, VLSI Fabrication Principles, 2nd ed., New York: Wiley-Interscience, pp. 487-495, 1994. [23] K. Wefers and C. Misra, Oxides and Hydroxides of Aluminum, Pittsburgh: Alcoa Research Laboratories, 1987, ch.5, sec.1, p.64. [24] Y. D. Tan, “Effect of Gate Metal Thickness on The 2-State Characteristics of MOS Structure with Ultrathin Oxide,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ. Taipei, Taiwan, R.O.C., Jun. 2015. [25] M. A. Siddiqi, Dynamic RAM: Technology Advancements, CRC Press, 2012. [26] J. M. Park et al., “20nm DRAM: A new beginning of another revolution,” 2015 IEEE International Electron Devices Meeting, Washington, DC, USA, pp. 26.5.1-16.5.4, Dec. 2015 [27] M. S. Akbar et al., “Investigation of transient relaxation under static and dynamic stress in Hf-based gate oxides,” IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1200-1207, May 2006. [28] SIA, “International technology roadmap for semiconductors (ITRS): 2015,” Semiconductor Industry Association (SIA), Washington, D.C., USA, Tech. Rep., table FEP4: DRAM Stacked Capacitor Technology Requirements, [Online]. Available: www.itrs2.net/ | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/73033 | - |
| dc.description.abstract | 本篇論文中，我們製備了具有不同氧化層厚度的邊緣環繞超薄金屬閘極金氧半穿隧二極體。此種結構元件的瞬間雙態特性可以被放大。在論文的第二章中，具有不同氧化層厚度的邊緣環繞超薄金屬閘極金氧半穿隧二極體以及傳統金氧半穿隧二極體的電特性和瞬間雙態特性，證明了邊緣環繞超薄金屬閘極金氧半穿隧二極體在適當的氧化物厚度範圍內可以呈現較大的雙態電流差值。邊緣環繞超薄金屬閘極金氧半穿隧二極體的電特性對氧化層厚度非常敏感。此外，電流-電壓遲滯現象與瞬間雙態特性由於元件邊緣處的RC延遲使得兩者密切相關。在論文的第三章中，比較了最佳氧化層厚度 (29Å) 的邊緣環繞超薄金屬閘極金氧半穿隧二極體以及傳統金氧半穿隧二極體的瞬間暫態特性。瞬間鬆弛現象證明了RC延遲的存在。此外，元件的信號維持時間為 190 毫秒，這達到了動態隨機存取記憶體維持時間 64 毫秒應用標準的要求。在論文的第四章中，透過調變超薄金屬閘極區域面積和脈衝電壓的操作，在調變脈衝偏壓下可以放大瞬間暫態的響應。至於其他的關係則需要再更進一步的研究。 | zh_TW |
| dc.description.abstract | In this thesis, ultrathin metal surrounded gate Metal-Insulator-Semiconductor (UTMSG MIS) tunnel diodes with various oxide thicknesses were fabricated. The transient two-state characteristics of targeting devices can be magnified. In chapter 2, the electrical characteristics and transient two-state characteristics in the UTMSG MIS and the regular gate Metal-Insulator-Semiconductor (RG MIS) tunnel diodes with various oxide thickness were demonstrated that the UTMSG MIS devices can maintain larger two-state current window within appropriate oxide thicknesses range. The electrical properties of the UTMSG MIS devices are very sensitive to oxide thickness. Besides, the I-V hysteresis is closely related to the transient two-state characteristics because of RC delay at edge. In chapter 3, the optimal oxide thickness (29 Å) for transient characteristics in the UTMSG MIS devices was studied by comparing the RG MIS devices. Transient relaxation proves the existence of the RC delay. Also, the retention time of the UTMSG MIS device reaches a value of 190 ms, which fulfills the requirement of the DRAM applications. In chapter 4, by modulating ultrathin metal area and programming operation, transient responses have been enlarged during bias operation. Other relationship should be further investigated in more detail. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T07:14:41Z (GMT). No. of bitstreams: 1 ntu-108-R06943071-1.pdf: 3954493 bytes, checksum: 5b6167a607e921ebce26abc47b402d06 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | Content
口試委員會審定書………………………..............…………………....……………I 誌謝……………………………………................…………………………………III 摘要…………………………………………………................……………………IV Abstract…………………………………………................……………..…………V Content……………………………………………..................……………………VI Table Caption………………………………………...............…………………..VIII Figure Caption……………………………………...............……………………...IX Chapter 1 Introduction……………………………….…………………..............…1 1-1 Motivation………………...………………………………..……………....…….1 1-2 Electrical characteristics of MIS (p) tunnel diode…………………………….3 1-3 Electrical determination of oxide thickness……………….…………………..5 1-4 Anodic oxidation system……………………………………………….….……6 1-5 The ultrathin aluminum and the native aluminum oxide…………………….8 1-6 Dynamic random access memory (DRAM) and embedded DRAM……..…8 Chapter 2 Electrical Characteristics of Ultra-thin Metal Surrounded Gate MIS(p) Tunnel Diode…………………………...........……………………….................…13 2-1 Introduction…………………………………………………...………........…..14 2-1-1 Overview…………………………………………………………....….....….14 2-1-2 Two-state current behavior……………………………………..……….....15 2-2 Experimental……………………………………………………………......….16 2-3 Results and discussion………………………………………………………..17 2-3-1 I-V and C-V characteristics…………………………………….......………17 2-3-2 Two-state characteristics………………………………………........……..18 2-3-3 Transient relaxation………………………………………………........……19 2-3-4 Relationship between I-V and the two-state characteristics…........……20 2-3-5 Write/Read mechanism……………………………………...…….....…….20 2-3-6 Oxide thickness effect mechanism………………..…..………….……..…22 2-4 Summary…………………………………………………………………......…24 Chapter 3 Optimal Oxide Thickness of Transient Characteristics in MIS(p) Tunnel Diode with Ultra-thin Metal Surrounded Gate….…….…......….....……41 3-1 Introduction………………………………………………………….….....……42 3-2 Results and discussion…………………………………….....……….………42 3-2-1 I-V and C-V characteristics………………………………..….…...………..42 3-2-2 Relationship between I-V characteristics and transient relaxation……..43 3-2-3 Two-state characteristics with pulse programming cycle operation…….46 3-2-4 Retention characteristics……………………………….......……………….47 3-3 Summary……………………………………………………………………......48 Chapter 4 Modulations of Ultra-thin Metal Area and Programming Operation………………………………….…………………...............…….……..59 4-1 Introduction…………………………………………………………….....…….59 4-2 Experimental……………………………………………….…………….….....60 4-3 Results and discussion………………………………………………………..61 4-3-1 The modulation of pulse programming cycle operation…………....……61 4-3-2 Two-state characteristics………………………......………………….……62 4-3-3 Retention characteristics……………………………………...….....….…..63 4-4 Summary…………………………………………………………….....……….64 Chapter 5 Conclusions and Future works………………….........………...…….69 5-1 Conclusions…………………………………………………………………......69 5-2 Future works……………………………………………………………......…..70 Reference………….……………………….……………………..............….…….71 | |
| dc.language.iso | en | |
| dc.subject | 超薄氧化層 | zh_TW |
| dc.subject | 記憶體 | zh_TW |
| dc.subject | 雙態特性 | zh_TW |
| dc.subject | 超薄金屬 | zh_TW |
| dc.subject | 金氧半穿隧二極體 | zh_TW |
| dc.subject | 嵌入式隨機存取記憶體 | zh_TW |
| dc.subject | 隨機存取記憶體 | zh_TW |
| dc.subject | MIS Tunnel diode | en |
| dc.subject | ultrathin metal | en |
| dc.subject | ultrathin oxide | en |
| dc.subject | embedded DRAM | en |
| dc.subject | DRAM | en |
| dc.subject | two-state characteristics | en |
| dc.subject | memory | en |
| dc.title | 氧化層厚度對邊緣環繞超薄金屬閘極金氧半穿隧二極體雙態特性之影響 | zh_TW |
| dc.title | Effect of Oxide Thickness on The Two-State haracteristics in MIS(p) Tunnel Diode with Ultra-thin Metal Surrounded Gate | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林浩雄(Hao-Hsiung Lin),林致廷(Chih-Ting Lin) | |
| dc.subject.keyword | 金氧半穿隧二極體,記憶體,雙態特性,隨機存取記憶體,嵌入式隨機存取記憶體,超薄氧化層,超薄金屬, | zh_TW |
| dc.subject.keyword | MIS Tunnel diode,memory,two-state characteristics,DRAM,embedded DRAM,ultrathin oxide,ultrathin metal, | en |
| dc.relation.page | 75 | |
| dc.identifier.doi | 10.6342/NTU201901102 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-07-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-108-1.pdf 未授權公開取用 | 3.86 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。