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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Chung-Yi Ting | en |
dc.contributor.author | 丁中一 | zh_TW |
dc.date.accessioned | 2021-06-17T07:10:19Z | - |
dc.date.available | 2029-07-22 | |
dc.date.copyright | 2019-07-24 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-07-22 | |
dc.identifier.citation | [1]P. Y. Wu, S. Y. S. Tsui, and P. K. T. Mok, “Area- and power-efficient monolithic buck converters with pseudo-type III compensation,” IEEE J. of Solid-State Circuits, vol. 45, no. 8, pp. 1446–1455, Aug. 2010.
[2]M. Ho, J. Guo, K. H. Mak, W. L. Goh, S. Bu, Y. Zheng, X. Tang, and K. N. Leung, “A CMOS low-dropout regulator with dominant-pole substitution,” IEEE Trans. on Power Electronics, vol. 31, no. 9, pp. 6362–6371, Sept. 2016. [3]J. Y. Lee, S. E. Kim, S. J. Song, J. K. Kim, S. Kim, and H. J. Yoo, “A regulated charge pump with small ripple voltage and fast start-up,” IEEE J. of Solid-State Circuits, vol. 41, no. 2, pp. 425–432, Feb. 2006. [4]K. H. Chen, Power Management Techniques for Integrated Circuit Design, NJ: John Wiley & Sons, 2016. [5]C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS dc-dc converter with on-chip current-sensing technique,” IEEE J. of Solid-State Circuits, vol. 39, no. 1, pp. 3–14, Jan. 2004. [6]R. Redl, and J. Sun, “Ripple-based control of switching regulators—An overview,” IEEE Trans. on Power Electronics, vol. 24, no. 12, pp. 2669–2680, Dec. 2009. [7]S. Tian, F. C. Lee, Q. Li, and Y. Yan, “Unified equivalent circuit model and optimal design of V2 controlled buck converters,” IEEE Trans. on Power Electronics, vol. 31, no. 2, pp. 1734–1744, Feb. 2016. [8]S. C. Huerta, A. Soto, P. Alou, J. A. Oliver, O García, and J. A. Cobos, ” Advanced control for very fast dc-dc converters based on hysteresis of the Cout current,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 60, no. 4, pp. 1052-1061, Apr. 2013. [9]F. Su, and W. H. Ki, “Digitally assisted quasi-V2 hysteretic buck converter with fixed frequency and without using large-ESR capacitor,” IEEE International Solid-State Circuits Conference (ISSCC), pp.446-447, Feb. 2009. [10]Y. Y. Yan, P. H. Liu, F. C. Lee, Q. Li, and S. Tian “V2 control with capacitor current ramp compensation using lossless capacitor current sensing,” IEEE Energy Conversion Congress and Exposition (ECCE), pp. 117 - 124, 15-19 Sept. 2013. [11]P. H. Liu, Y. Y. Yan, F. C. Lee, and Q. Li, “Auto-tuning and self-calibration techniques for V2 control with capacitor current ramp compensation using lossless capacitor current sensing,” IEEE Energy Conversion Congress and Exposition (ECCE), pp. 1105 - 1112, 14-18 Sept. 2014. [12]Y. Yan, F. C. Lee, S. Tian, and P. H. Liu, “Modeling and design optimization of capacitor current ramp compensated constant on-time V2 control,” IEEE Trans. on Power Electronics, vol. 33, no. 8, pp. 7288-7296, Aug. 2018. [13]F. Su, W. H. T. Ki, and C. Y. Tsui, “Ultra fast fixed-frequency hysteretic buck converter with maximum charging current control and adaptive delay compensation for DVS applications,” IEEE J. of Solid-State Circuits, vol. 43, no. 4, pp. 815–822, Jan. 2008. [14]P. Li, L. Xue, P. Hazucha, T. Karnik, R. Bashirullah, “A delay-locked synchronization scheme for high-frequency multiphase hysteretic dc-dc converters,” IEEE J. of Solid-State Circuits, vol. 44, no. 11, pp. 3131-3145, Nov. 2009. [15]C. Huang, P. K. T. Mok, “A 100 MHz 82.4% efficiency package-bondwire based four-phase fully-integrated buck converter with flying capacitor for area reduction,” IEEE J. of Solid-State Circuits, vol. 47, no. 6, pp. 2977-2988, Dec. 2013. [16]Y. S. Roh, Y. J. Moon, J. Park, M. G. Jeong ,and C. Yoo, “A multiphase synchronous buck converter with a fully integrated current balancing scheme,” IEEE Trans. on Power Electronics, vol. 30, no. 9, pp.5159-5169, Sept. 2015. [17]M. Sun, Z. Yang, K. Joshi, D. Mandal, P. Adell, and B. Bakkaloglu “A 6A, 93% peak efficiency, 4-phase digitally synchronized hysteretic buck converter with ±1.5% frequency and ±3.6% current-sharing error,” IEEE J. of Solid-State Circuits, vol. 47, no. 12, pp. 3081-3093, Nov. 2017. [18]M. K. Song, L.Chen, J. Sankman, S. Terry, D. Ma, “A 20V 8.4W 20MHz four-phase GaN dc-dc converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constant propagation delay and 1ns switching rise time,” IEEE International Solid-State Circuits Conference (ISSCC), pp.74-75, Feb. 2015. [19]B. Choi, Pulsewidth Modulated DC-DC Power Conversion: Circuits, Dynamics, and Control Designs, NJ: IEEE Press, 2013. [20]R. B. Ridley, “A new, continuous-time model for current-mode control,” IEEE Trans. on Power Electronics, vol. 6, no. 2, pp.271-280, Apr. 1991. [21]S. Bari, Q. Li, and F. C. Lee, “A new fast adaptive on-time control for transient response improvement in constant on-time control,” IEEE Trans. on Power Electronics, vol. 33, no. 3, pp.2680-2689, Mar. 2018. [22]O. Garcia, P. Zumel, A. de Castro, and J. A. Cobos, “Effect of the tolerances in multi-phase dc-dc converters,” 2005 IEEE 36th Power Electronics Specialists Conference, pp. 1452 - 1457, 2005. [23]F. Pareschi, R. Rovatti, and G. Setti, “EMI reduction via spread spectrum in dc/dc converters: state of the art, optimization, and tradeoffs,” IEEE Access, vol. 3, pp. 2857-2874, Dec. 2015. [24]Y. H. Lee, Y. Y. Yang, K. H. Chen, Y. H. Lin, S. J. Wang, K. L. Zheng, P. F. Chen, C. Y. Hsieh, Y. Z. Ke, Y. K. Chen, and C. C. Huang, “A DVS embedded power management for high efficiency integrated SoC in UWB system,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2227-2238, Nov. 2010. [25]S. H. Chien, T. H. Hung, S. Y. Huang, and T. H. Kuo, “A monolithic capacitor-current-controlled hysteretic buck converter with transient-optimized feedback circuit,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2524-2532, Nov. 2015. [26]C. H. Tsai, S. M. Lin, and C. S. Huang, “A fast-transient quasi-V2 switching buck regulator using AOT control with a load current correction (LCC) technique,” IEEE Trans. on Power Electronics, vol. 28, no. 8, pp. 3949-3957, Aug. 2013. [27]K. Y. Hu, S. M. Lin, and C. H. Tsai, “A fixed-frequency quasi-V2 hysteretic buck converter with PLL-based two-stage adaptive window control,” IEEE Trans. on Circuits and Systems I, vol. 62, no. 10, pp. 2565-2573, Oct. 2015. [28]J. J. Chen, Y. S. Hwang, C. H. Chang, Y. T. Ku, and C. C. Yu “A sub-1 μs fast-response buck converter with adaptive and frequency-locked controlled technique,” IEEE Trans. on Industrial Electronics, vol. 66, no. 3, pp. 2198-2203, Mar. 2019. [29]D. H. Jung, K. Kim, S. Joo, and S. O. Jung, “0.293-mm2 fast transient response hysteretic quasi-V2 dc-dc converter with area-efficient time-domain-based controller in 0.35-μm CMOS,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1844-1855, Jun. 2018. [30]Y. C. Hsu, C. Y. Ting, J. Y. Lin, and Charlie C. P. Chen, “A transient enhancement dc-dc buck converter with dual operating modes control technique,” IEEE Trans. on Circuits and Systems II Express Briefs, accept for publication. 2018. [31]K. I. Wu, B. T. Hwang, and C. C. P. Chen, “Synchronous double-pumping technique for integrated current-mode PWM dc–dc converters demand on fast-transient response,” IEEE Trans. on Power Electronics, vol. 32, no. 1, pp. 849-865, Jan. 2017. [32]l. Cheng, Y. Liu, and W. H. Ki, “A 10/30 MHz fast reference-tracking buck converter with DDA-based type-III compensator,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2788-2799, Dec. 2014. [33]R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation. Piscataway, NJ: IEEE Press, 1998, Chap 26. [34]S. S. Kudva and R. Harjani, “Fully-integrated on-chip DC-DC converter with a 450X output Range,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1940-1951, Aug. 2011. [35]Y. W. Huang, T. H. Kuo, S. Y. Huang, and K. Y. Fang, “A four-phase buck converter with capacitor-current-sensor calibration for load-transient-response optimization that reduces undershoot/overshoot and shortens settling time to near their theoretical limits,” IEEE J. of Solid-State Circuits, vol. 53, no. 2, pp. 552-568, Feb. 2018. [36]B. Lee, M. K. Song, A. Maity, and D. B. Ma, “A 25 MHz 4-phase saw hysteretic dc-dc converter with 1-cycle apc achieving 190 ns settle to 4 a load transient and above 80% efficiency in 96.7% of the power range,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017, pp. 190–191. [37]P. J. Liu, J. N. Tai, J. H. Chen, and Y. J. Chen, “Spur-reduction design of frequency-hopping dc-dc converters,” IEEE Trans. on Power Electronics, vol. 27, no. 11, pp.4763-4770, Nov. 2012. [38]C. Tao, and A. A. Fayed, “PWM control architecture with constant cycle frequency hopping and phase chopping for spur-free operation in buck regulator,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 9, pp.1596-1607, Sept. 2013. [39]W. R. Liou, M. L. Yeh, P.S. Chen, C. C. Tseng, T. Y. Huang, S.C. Lin, C. Y. Lin, and C. H. Sun, “Monolithic low-EMI CMOS dc-dc boost converter for portable applications,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp.420-424, Feb. 2014. [40]Y. J. Park, J. H. Park, H. J. Kim, H. Ryu, S. Y. Kim, Y. G. Pu, K. C. Heang, Y. Yang, M. Lee, and K. Y. Lee, “A design of a 92.4% efficiency triple mode control dc-dc buck converter with low power retention mode and adaptive zero current detector for IoT/wearable applications,” IEEE Trans. on Power Electronics, vol. 32, no. 9, pp.6946-6960, Sept. 2017. [41]X. Ke, J. Sankman, Y. Chen, L. He, and D. B. Ma, “A tri-slope gate driving GaN dc-dc converter with spurious noise compression and ringing suppression for automotive applications,” IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp.247-260, Sept. 2017. [42]S. H. Pakala, P. R. Surkanti, and P. M. Furth, “A spread-spectrum mode enabled ripple-based buck converter using a clockless frequency control,” IEEE Trans. on Circuits and Systems ΙΙ: Express Briefs, vol. 66, no. 3, pp. 382-386, Mar. 2019. [43]M. Nashed, and A. A. Fayed, “Current-mode hysteretic buck converter with spur-free control for variable switching noise mitigation,” IEEE Trans. on Power Electronics, vol. 33, no. 1, pp.650-664, Jan. 2018. [44]Y. S. Hwang, J. J. Chen, B. H. Lai, Y. T. Ku, and C. C. Yu “A fast-transient boost converter with noise reduction techniques for wireless sensor networks,” IEEE Sensors Journal, vol. 16, no. 9, pp.3188-3197, May 2016. [45]Y. S. Hwang, J. J. Chen, W. J. Hou, P. H. Liao, and Y. T. Ku “A 10-μs transient recovery time low-EMI dc-dc buck converter with ∆-Σ modulator,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 9, pp.2983-2992, Sept. 2016. [46]J. J. Chen, Y. S. Hwang, C. S. Jheng, Y. T. Ku, and C. C. Yu, “A low-EMI buck converter with continuous-time delta-sigma-modulation and burst-mode techniques,” IEEE Trans. on Industrial Electronics, vol. 65, no. 9, pp.6860-6869, Jan. 2018. [47]J. Sun, “Small-signal modeling of variable-frequency pulsewidth modulators,” IEEE Trans. on Aerospace and Electronic Systems, vol. 38, no. 3, pp.1104-1108, Dec. 2002. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/72918 | - |
dc.description.abstract | 科技日新月異,像是5G通訊、大數據、物聯網、人工智慧興起。未來,各種不同應用會大量需要高速電腦運算能力與高速資料傳輸速度。因此,高速類比與數位電路在高速運算與高速傳輸介面扮演關鍵角色。根據摩爾定律發展,半導體製程技術不斷進步,使得電路的供應電壓不斷往下降。為了提升性能,電子元件的功耗卻不斷上升。因此,近年來應用於低電壓大電流負載直流-直流轉換器成為研究重點。在低電壓大電流應用下,負載可區分為高速數位電路與高速類比電路兩種。高速數位電路有中央處理器(CPUs)、圖形處理器(GPUs)、人工智慧運算晶片(AI chips)等;而高速類比電路有高速無線傳輸器(High-speed RF transmitters)、高速無線接收器(High-speed RF receivers)、高速數位類比轉換器(High-speed digital-to-analog converters)、高速類比數位轉換器(High-speed analog-to-digital converters)、光通訊電路(Optical communication circuits)等。這些高速電路需要具快速的暫態響應、低電磁干擾、大電流承載能力、與高轉換效率的直流-直流轉換器。傳統解決方案使用線性穩壓器(Low dropout regulators),達到快速暫態響應能力、與低漣波輸出(Low-ripple output voltage)的電源。但線性穩壓器不適合高功率應用,而且線性穩壓器受限於最小電壓差(Dropout voltage),會導致在高功率應用下轉換效率不高。為了在高功率應用下達到快速暫態響應、快速動態調節響應、大電流承載能力、高轉換效率、與低電磁干擾,本論文聚焦於低電壓大電流負載的直流-直流轉換器之電源管理技術相關研究。本論文所發展的電源管理技術有以下三個部份:
第一部份為了提升直流-直流轉換器的暫態響應速度與動態電壓調整響應速度,因此提出應用於射頻電路下最適定導通時間控制之類電壓平方磁滯控制降壓型直流-直流轉換器。為了實現最適定導通時間控制(Adaptive constant on-time control),本論文提出具暫態加速技術的最適定導通時間電路,並對系統補償進行最佳化,以達到高速暫態響應與高速動態電壓調整響應。本晶片採用台積電T18 1P6M製程,面積1.81mm2,最高轉換效率為90.1%。藉由晶片量測結果,當負載電流往上變化600mA,回復時間為0.6μs;當負載電流往下變化600mA,回復時間為0.6μs。而參考電壓從1.8跳升到2.4V,輸出電壓響應速度為2μs;參考電壓從2.4V跳降1.8V,輸出電壓響應速度為2μs。 第二部份為了提高直流-直流轉換器的電流承載能力與轉換效率,因此提出具電感電流均流校正技術之快速延遲鎖定迴路應用於固定導通時間控制之四相位降壓型直流-直流轉換器。本晶片除了採用類電壓平方控制與固定導通時間調變之外,也採用延遲相位鎖定迴路產生四相位的脈波控制訊號且彼此錯相九十度,達到低漣波輸出電壓。為了達到快速暫態響應能力,本研究提出一組自動切換單/雙向觸發相位偵測器(Automatically switching single/dual triggered phase detector)應用於快速延遲鎖定迴路(Fast-locking delay-locked loop)。此外,為了解決主、被動元件的非理想效應所造成多相位電感電流不均流問題,本論文提出脈波縮減電路(Pulse-width-shrunk technique)進行均流背景校正。本晶片使用台積電T18 1P6M製程,面積6.17mm2。最後透過後模擬驗證結果,當負載電流往上變化1.4A,回復時間與電壓降為2.5μs/6.5mV;當負載電流往下變化1.4A,回復時間與電壓升為2.5μs/8mV。因為四相位均流且正確錯相九十度,最高效率達85%且輸出電壓漣波為4mV。 第三部份為了解決電磁干擾問題,因此提出具抗電磁干擾之類電壓平方磁滯控制降壓型直流-直流轉換器。傳統類電壓磁滯控制降壓型轉換器可視為一組壓控振盪器(Voltage control oscillator)。為了定頻控制,將傳統類電壓磁滯控制降壓型轉換器結合鎖相控制迴路。本論文的抗電磁干擾技術是整合鎖相控制迴路(Phase-locked loop)與全數位二級一階和差積分調變器(MASH 1-1 all-digital Δ-Σ modulator),將脈波控制訊號的頻率進行調變,使得輸出電壓頻譜達到展頻效果。此晶片採用台積電T18 1P6M製程,面積1.81mm2,最高轉換效率為90%。透過後模擬驗證,展頻前後頻譜改善20dB。當負載電流往上變化500mA,回復時間與電壓降為4.47μs/34.3mV;當負載電流往下變化500mA,回復時間與電壓降 5.12μs /32.3mV。 | zh_TW |
dc.description.abstract | Science and technology rapidly progress day by day, such as 5G communication, big data, internet-of-things (IoT), artificial intelligence (AI). In the future, these computers with high-speed computing ability and high-speed data transmission are needed in various applications. Therefore, high-speed integrated circuits are very important in high-speed computing and data transmission interface. In addition, the supply voltage becomes lower and lower because the technology process is rapidly advancement based on Moore’s law. However, power consumption of electronic devices constantly increase for higher performance. Thus, these DC-DC converters in low-voltage and high-current applications are essential research topic in recent years. In low-voltage and high-current applications, these loads have two categories about high-speed digital circuits such as CPUs, GPUs, and AI chips and high-speed analog circuits such as high-speed RF transmitters, high-speed RF receivers, high-speed DACs, high-speed ADCs, and optical communication circuits. In general, these high-speed circuits need to the DC-DC converter with fast load-transient response, low EMI, high-current capability, and high-efficiency. Traditionally, low-dropout regulators (LDOs) have been used in on-chip voltage source because of load-transient response and low-ripple output voltage. However, LDOs are not suitable for high power applications because the dropout voltage leads to low efficiency in low-voltage and high-current applications. To achieve fast load-transient response, fast DVS tracking response, high-current capability, high power efficiency, and low EMI in high power application, the dissertation focuses on studying power management techniques of these DC-DC converters in low-voltage and high-current applications. The dissertation has three works:
In the first work, we propose a quasi-V2 hysteretic buck converter with adaptive constant on-time (ACOT) control for fast DVS and load-transient response in RF applications. For implement adaptive constant on-time control, the work proposes adaptive constant on-time circuit with transient-enhanced technique and optimization of system compensation for fast load-transient response and fast DVS. The work uses TSMC T18 1P6M process and chip area is 1.81mm2. The measured peak efficiency is 90.1%. In 600mA step-up/down load current, the light-to-heavy/heavy-to-light recovery time is 0.6μs. In 0.6V voltage step-up/down, the up-tracking/down-tracking time of DVS is 2μs. In the second work, we propose an inductor current-balancing technique (ICBT) for fast-locking delay-locked loop (FL-DLL) based four-phase buck converter with constant on-time control to achieve high-current capability and power efficiency in low-voltage and high-current applications. The work uses quasi-V2 control and constant on-time modulator for transient response and light-load efficiency. Moreover, the work proposes a fast-locking delay-locked loop (FL-DLL) for generating four-phase control signals with phase difference 90 degree and achieving low-ripple output voltage. In FL-DLL, we proposes automatic switching single/dual triggered phase detector (ASS/DT-PD) for achieving fast load-transient response. Furthermore, non-ideal effects of active and passive components causes inductor current in-balance issue. Therefore, the work proposes pulse-width-shrunk technique (PWST) automatically calibrate four-phase control signals to achieve current balance in every phase. The work uses TSMC T18 1P6M process and chip area is 6.17mm2. Finally, these proposed techniques can be verified by post-layout simulation. In 1.4A step-up/down load current, the light-to-heavy/heavy-to-light recovery time is 2.5μs/2.5μs and undershoot/overshoot voltage is below 10mV. Because of achieving current balance and phase alignment, the proposed FL-DLL based four-phase buck converter has 85% efficiency and 4mV voltage ripple. In the third work, we propose a quasi-V2 hysteretic buck converter with EMI reducing technique using phased-locked loop with MASH 1-1 all-digital Δ-Σ modulator. The hysteretic DC-DC buck converter is viewed as voltage control oscillator (VCO). For keeping fixed-frequency, the work uses phase-locked loop to lock PWM frequency. In the EMI reducing technique, phase-locked loop with MASH 1-1 all-digital Δ-Σ modulator randomly modulates PWM control signal for spreading spectrum of output voltage. The chip uses TSMC T18 1P6M process and chip area is 1.81mm2. Moreover, the measured peak efficiency is 90%. By post-layout simulation, the low EMI reducing technique improves 20dB compared with without EMI technique. In load-transient response performance, the light-to-heavy recovery time is 4.47μs and undershoot voltage is 34.3mV and the heavy-to-light recovery time is 5.12μs and overshoot voltage is 32.3mV. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T07:10:19Z (GMT). No. of bitstreams: 1 ntu-108-D01943002-1.pdf: 13434707 bytes, checksum: 97425c54f7ae63ae12773a2f8b42f41c (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 口試委員會審定書………………………………...……………………......... I
誌謝……………………………………………….………………..………..... II 中文摘要………………………………………………………….................... III ABSTRACT……...……………………..………………………….................. VI Contents……...……………………..……………...………………………….. IX List of Figures….....……………………..…………………………………….. XII List of Tables……...……………………..………………….…………………. XXI 1. Introduction………………………………………………………… 1 1.1 Introduction of Low-voltage and High-current Loads………. 1 1.2 Fundamental of DC-DC Converters…………………………. 3 1.2.1 Topology of DC-DC Converters………………………. 3 1.2.2 Control Methods of SWP DC-DC Converters………… 5 1.2.3 Compensators of SWP DC-DC Converters……………. 19 1.3 Constant On-time Control Issue……………………………... 25 1.4 Multi-phase Control Issue………...…………………………. 26 1.5 Electromagnetic Interference (EMI) Issue…………………... 27 1.6 Research Goals and Contributions…………………………... 28 1.7 Dissertation Organization……………………………………. 32 2. A Quasi-V2 Hysteretic Buck Converter with Adaptive COT Control for Fast DVS and Load-transient Response in RF Applications………………………………………………………… 34 2.1 Introduction………………………………………………….. 34 2.2 Analysis of Previous Fast-transient Techniques…………....... 35 2.3 Proposed System Architecture and Operation Principle…….. 42 2.3.1 System Architecture…………………………………. 42 2.3.2 Operational Principle………………………………... 43 2.4 Generalized Design Methodology and the System Stability… 47 2.4.1 Design Methodology……………………………….... 47 2.4.2 System Stability and Simulation Results……………. 48 2.5 Circuit Implementation of the Basic Building Blocks………. 52 2.5.1 High-bandwidth Comparator………………………... 52 2.5.2 Hysteretic Comparator………………………………. 53 2.5.3 OTA-based Error Amplifier (OTA-EA)……………... 54 2.5.4 Two-bounded Circuit………………………………... 55 2.5.5 Soft-start Circuit……………………………………... 55 2.5.6 Power MOSs and Buffer with Dead-time Circuit…… 57 2.6 Transistor Level Simulation Results………………………… 58 2.6.1 Load Transient Response Pre-simulation……………. 58 2.6.2 Dynamic Voltage Scaling Pre-simulation……………. 61 2.6.3 Pre-simulation Summary…………………………….. 65 2.6.4 Load Transient Response Post-simulation…………... 66 2.6.5 Dynamic Voltage Scaling Post-simulation…………... 69 2.6.6 Post-simulation Summary…………………………… 73 2.7 Experimental Measured Results……………………………... 73 2.8 Conclusion…………………………………………………… 78 3. An Inductor Current-balancing Technique (ICBT) for Fast-locking Delay-locked Loop (FL-DLL) Based Four-phase Buck Converter with Constant On-time Control (COT) for Load-transient Response…………………………………………... 80 3.1 Introduction………………………………………………….. 80 3.2 Analysis of Previous Inductor Current-balancing Technique.. 82 3.3 Proposed System Architecture and Operation Principle…….. 86 3.3.1 System Architecture…………………………………… 86 3.3.2 Operation Principle……………………………………. 87 3.4 Circuits Implementation of the Basic Building Blocks……… 96 3.4.3 Voltage-controlled Delay Line and Delay Cell……… 96 3.4.4 Charge Pump (CP) with Low Pass Filter (LPF)……... 97 3.4.5 Pulse-width-shrunk Technique (PWST)……………... 97 3.5 Transistor Level Simulation Results………………………… 99 3.5.1 Inductor Current-balancing Pre-simulation……………. 99 3.5.2 Load-transient Response Pre-simulation………………. 102 3.5.3 Pre-simulation Summary………………………………. 105 3.5.4 Inductor Current-balancing Post-simulation…………... 105 3.5.5 Load-transient Response Post-simulation……………... 108 3.5.6 Post-simulation Summary…...………………………… 112 3.6 Experimental Measured Results……………………………... 112 3.7 Conclusion…………………………………………………… 117 4. A Quasi-V2 Hysteretic Buck Converter with EMI Reducing Technique Using PLL with MASH 1-1 All-digital Delta-sigma Modulator……………………...……………………………………. 118 4.1 Introduction………………………………………………….. 118 4.2 Analysis of Previous EMI Reducing Techniques……………. 119 4.3 Proposed System Architecture and Stability Analysis………. 120 4.3.1 System Architecture…………………………………. 120 4.3.2 Stability Analysis…………………………………….. 123 4.4 Circuit Implementation of the Basic Building Blocks………. 125 4.4.1 Multi-modulus Divider………………………………. 125 4.4.2 MASH 1-1 All-digital Delta-sigma Modulator…….... 125 4.4.3 Two-bounded Circuit………………………………… 127 4.5 Transistor Level Simulation Results………………………… 128 4.5.1 Pre-simulation of EMI Reducing Technique………… 128 4.5.2 Pre-simulation of Load-transient Response…………. 130 4.5.3 Pre-simulation Summary…………………………….. 133 4.5.4 Post-simulation of EMI Reducing Technique……….. 134 4.5.5 Pre-simulation of Load-transient Response…………. 134 4.5.6 Post-simulation Summary…………………………… 138 4.7 Experimental Measured Results……………………………... 139 4.8 Conclusion…………………………………………………… 142 5. Conclusion and Future Works…………………………………….. 144 5.1 Conclusion…………………………………………………… 144 5.2 Future Works………………………………………………… 145 Bibliography…………………………………………………………………... 147 Publication List…..…………………………………………………………..... 156 About the Author………………………………………………………………. 157 | |
dc.language.iso | en | |
dc.title | 應用於低電壓大電流負載的直流-直流轉換器之電源管理技術 | zh_TW |
dc.title | Power Management Techniques in DC-DC Converters for Low-voltage and High-current Loads | en |
dc.type | Thesis | |
dc.date.schoolyear | 107-2 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 趙昌博(Paul Chang-Po Chao),羅有綱(Yu-Kang Lo),邱煌仁(Huang-Jen Chiu),林景源(Jing-Yuan Lin),陳景然(Ching-Jan Chen) | |
dc.subject.keyword | 低電壓大電流負載,固定導通時間控制,類電壓平方磁滯控制,多相位直流-直流降壓型轉換器,電感電流均流校正技術,全數位二級一階和差積分調變器, | zh_TW |
dc.subject.keyword | Low-voltage and high-current loads,Constant on-time control,Quasi-V2 hysteretic control,Multi-phase DC-DC buck converter,Inductor current-balancing calibration technique,MASH 1-1 all-digital Δ-Σ Modulator, | en |
dc.relation.page | 156 | |
dc.identifier.doi | 10.6342/NTU201901716 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2019-07-22 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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