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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/72661完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Tzu-Yu Huang | en |
| dc.contributor.author | 黃子育 | zh_TW |
| dc.date.accessioned | 2021-06-17T07:03:01Z | - |
| dc.date.available | 2026-01-01 | |
| dc.date.copyright | 2021-03-11 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2021-01-14 | |
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[22] Nicolas Butzen, Michiel Steyaert, “A 1.1W/mm2-Power-Density 82%-Efficiency Fully Integrated 3:1 Switched-Capacitor DC-DC Converter in Baseline 28nm CMOS Using Stage Outphasing and Multiphase Soft-Charging,” ISSCC Papers, pp. 178–179, Feb. 2017. [23] D. El-Damak, S. Bandyopadhyay, and A. P. Chandrakasan, “A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 374–375. [24] Nicolas Butzen and Michiel Steyaert, “MIMO Switched-Capacitor Converter using only Parasitic Capacitance with Scalable Parasitic Charge Redistribution,” in Proc. IEEE ESSCIRC Conf., pp. 445–448, Nov. 2016. [25] Y. Lu, J. Jiang, and W.-H. Ki, “A multiphase switched-capacitor DC-DC converter ring with fast transient response and small ripple,” IEEE J. Solid-State Circuits, vol. 52, no. 2, pp. 579–591, Feb. 2017. [26] J. Delos, T. Lopez, E. Alarcn, and M. A. M. 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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/72661 | - |
| dc.description.abstract | 隨著物聯網的蓬勃發展，許多應用於物聯網裝置的晶片便順勢而生，此時如何有效率的提供電力給物聯網晶片成為了一項重要的議題，而低成本小體積的直流電壓轉換器是一種非常有競爭力的解決方法，全電容式的直流電壓轉換器因為其體積與功率密度比起電感式的直流電壓轉換器更具有優勢而更有機會達到此需求。在物聯網的應用上，大部分的裝置長時間都處於待機模式(Sleep mode)，直流電壓轉換器輕載時的轉換效率大大地影響著產品的使用時間，輕載轉換效率也成為全電容式電壓轉換器設計的難題。 本篇結合適應性開關調變機制和自主優化頻率調變技術，當負載改變時，兩項技術會追蹤負載情況並調整開關大小和時脈產生器的輸出頻率，以達到最高的轉換效率。適應性開關調變機制將開關切分為不同大小，依據當前的負載電流情況來決定要使用的開關大小，有效降低閘極驅動損耗。自主優化頻率調變技術則是依據負載情況改變時脈產生器的輸出頻率，透過此技巧，控制電路的功率耗損在輕載時可以被減輕。在功率級的設計中，當輸入為5V時本篇使用2.5V元件來降低閘極驅動損耗以及開關所需要的整體面積，並利用位準轉換器來確保開關元件不會因為過壓而損壞且具有足夠小的導通阻抗。 透過台積電0.25μm 1P3M High Voltage Mixed Signal CMOS製程實現，這個晶片將5伏特輸入轉換成固定的1.5伏特輸出，負載電流範圍從10微安培(μA)到10豪安培(mA)，輸出範圍為1000倍，在瞬間抽載時，暫態反應時間約為0.5μs，最高效率為75%，輕載效率為68%，適應性開關調變機制增進21%整體效率而自主優化頻率調變技術增進42%整體效率當負載電流為10微安培時，在所有的負載電流範圍內效率皆能保持70%左右。 | zh_TW |
| dc.description.abstract | In recent years, IoT (Internet of Things) thrives. Many chips for IoT applications are needed and designed. And the power management IC becomes an important topic for IoT due to its long sleep time. The SC DC-DC converters is a competitive solution for IoT. Its small area cost and power density are more suitable than the use of an inductive DC-DC converter. The long sleep time of IoT applications is the key issue for improving the product lifetime. To achieve high light-load efficiency is a critical problem for the DC-DC converter. This work combines the adaptive switch modulation (ASM) and self-optimized frequency modulation (SFM) technique for maximum efficiency tracking when the load condition changes. ASM technique separates the switches into different sizes. It changes the switches’ sizes depends on the load current condition, which decreases the gate driving loss effectively. SFM technique tracks the load condition and adjusts the output frequency of the clock generators. The control circuit power is reduced through the SFM technique in a light-load condition. The power stage is implemented with 2.5V devices that lessen the gate driving loss and the switches’ area when the input voltage is 5V. The 2.5V devices are used with a level shifter to prevent the junction breakdown and have low on-state resistance switches. This chip is implemented in the TSMC 0.25μm 1P3M High Voltage Mixed-Signal CMOS process. This converter provides a fixed output voltage of 1.5V when the input voltage is 5V. The load current is 10μA~10mA. The output range is 1000 times. The load transient response time is 0.5μs. The peak efficiency is 75%. The light-load efficiency is 68%. ASM technique improves 21% overall efficiency, and SFM technique improves 42% overall efficiency when the load current is 10μA. The efficiency maintains almost 70% in the whole load current range. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T07:03:01Z (GMT). No. of bitstreams: 1 U0001-1101202112242600.pdf: 4632154 bytes, checksum: 9f57bce7b403b749b65b90c1c6ce3ab3 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 口試委員會審定書 # 誌謝 i 摘要 ii ABSTRACT iii CONTENTS v LIST OF FIGURES viii LIST OF TABLES xii Chapter 1 Introduction 1 1.1 Motivation 3 1.2 Thesis Organization 5 Chapter 2 Fundamentals Analysis of Switched-Capacitor DC-DC Converter 6 2.1 Introduction 6 2.1.1 Architecture of Switched-Capacitor DC-DC Converter 8 2.1.2 Operation of Switched-Capacitor DC-DC Converter 9 2.2 Modeling of Switched-Capacitor DC-DC Converter 10 2.2.1 Slow Switching Limit Impedance 10 2.2.2 Fast-Switching Limit Impedance 14 2.2.3 Total Output Impedance 15 2.2.4 Gate Driving Loss 17 2.2.5 Parasitic Plate Capacitor Loss 17 2.2.6 Model of Switched-Capacitor DC-DC Converter 20 2.3 Control Technique of Switched-Capacitor DC-DC Converter 21 2.3.1 Pulse Frequency Modulation 21 2.3.2 Capacitance Modulation 24 2.3.3 Pulse Width Modulation 25 2.4 Clock Generator 26 2.4.1 LC Oscillator 28 2.4.2 Ring Oscillator 29 2.4.3 Relaxation Oscillator 31 Chapter 3 Wide-Output-Range Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Self-Optimized Frequency Modulation Techniques 33 3.1 Conventional Switched-Capacitor DC-DC Converter 33 3.2 Proposed Wide-Output-Range Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Self-Optimized Frequency Modulation Techniques 38 3.2.1 Adaptive Switch Modulation (ASM) 39 3.2.2 Self-Optimized Frequency Modulation (SFM) 41 3.2.3 Operation Principle 44 3.3 Design Goal 46 Chapter 4 Circuit Implementation 47 4.1 Architecture 47 4.1.1 Segmented Power stage 48 4.1.2 Low Voltage MOS Switch with Level Shifter 49 4.1.3 Pulse Frequency Modulation controller 52 4.1.4 Digital-Controlled Ring Oscillator 54 4.1.5 Low Power Relaxation Oscillator 57 4.2 Simulation results 63 4.2.1 Steady-state waveforms 63 4.2.2 Load Transient Response 64 4.2.3 Power efficiency 66 Chapter 5 Measurement Result 68 5.1 Chip Micrograph 68 5.2 Experimental Setup 70 5.3 Experimental Results 72 5.3.1 Steady-State Waveforms 72 5.3.2 Transient Waveforms 75 5.3.3 Power Efficiency 77 5.3.4 Performance Summary 80 Chapter 6 Conclusion and Future Work 84 6.1 Conclusions 84 6.2 Future Work 84 REFERENCE 86 | |
| dc.language.iso | en | |
| dc.subject | 大輸出範圍 | zh_TW |
| dc.subject | 適應性開關調變機制 | zh_TW |
| dc.subject | 自主優化頻率調變技術 | zh_TW |
| dc.subject | 全電容式直流電壓轉換器 | zh_TW |
| dc.subject | Adaptive Switch Modulation Technique | en |
| dc.subject | Switched-Capacitor DC-DC converter | en |
| dc.subject | Self-Optimized Frequency Modulation Technique | en |
| dc.subject | Wide-Output-Range | en |
| dc.title | 使用適應性開關調變與自主優化頻率調變技術且具有大範圍輸出的切換式電容直流轉換器 | zh_TW |
| dc.title | A Wide-Output-Range Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Self-Optimized Frequency Modulation Techniques | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 109-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳文中(Wen-Jung Wu),陳景然(Ching-Jan Chen),劉宗德(Tsung-Te Liu) | |
| dc.subject.keyword | 全電容式直流電壓轉換器,適應性開關調變機制,自主優化頻率調變技術,大輸出範圍, | zh_TW |
| dc.subject.keyword | Switched-Capacitor DC-DC converter,Adaptive Switch Modulation Technique,Self-Optimized Frequency Modulation Technique,Wide-Output-Range, | en |
| dc.relation.page | 92 | |
| dc.identifier.doi | 10.6342/NTU202100041 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2021-01-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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