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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Hsiu-Hsien Ting | en |
| dc.contributor.author | 丁修賢 | zh_TW |
| dc.date.accessioned | 2021-06-17T07:02:05Z | - |
| dc.date.available | 2019-08-05 | |
| dc.date.copyright | 2019-08-05 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-07-31 | |
| dc.identifier.citation | [1] Shilei Hao, Tongning Hu, and Qun Jane Gu, “A CMOS Phase Noise Filter With Passive Delay Line and PD/CP-Based Frequency Discriminator”, IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 7, pp. 4154-4164, November 2017.
[2] Zhiqiang Huang, Bingwei Jiang, and Howard C. Luong, “A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector”, IEEE Transactions on Circuit and System I: Regular Papers, vol. 65, no. 7, pp. 2118-2126, July 2018. [3] Alvin Li, Yue Chao, Xuan Chen, Liang Wu, and Howard C. Luong, “A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs”, IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2128-2140, August 2017. [4] Seungkee Min, Tino Copani, Sayfe Kiaei, and Bertan Bakkaloglu, “A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation”, IEEE Journal of Solid-State Circuits, vol. 48, no. 5, pp. 1151-1160, May 2013. [5] Shravan S. Nagam, and Peter R. Kinget, “A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector”, IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 703-714, March 2018. [6] SeongHwan Cho, “Self-noise cancelling techniques for voltage-controlled oscillators” IEEE Electronic Letter, vol. 44, no. 25, pp. 1436-1437, December 2008. [7] Dongin Kim, and SeongHwan Cho, “A Supply Noise Insensitive PLL with a Rail-to-Rail Swing Ring Oscillator and a Wideband Noise Suppression Loop” IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. C180-181, 2017. [8] Xiang Gao, Eric Klumperink, Paul F. J. Geraedts, and Bram Nauta, “Jitter analysis and a benchmarking figure-of-merit for phase-locked loops” IEEE Transactions on Circuits and System II: Express Briefs, vol. 56, no. 2, pp. 117–121, February, 2009 [9] Xiang Gao, Eric Klumperink, Mounir Bohsali, and Bram Nauta, “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N^2”, IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, December 2009. [10] Xiang Gao, Eric Klumperink, and Bram Nauta, “Sub-Sampling PLL Techniques”, IEEE Custom Integrated Circuits Conference(CICC), pp. 1-8, September 2015. [11] Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong-Joong Kim, and Pavan Kumar Hanumolu, “A 0.0021〖mm〗^2 1.82mW 2.2GHz PLL Using Time-Based Integral Control in 65nm CMOS,” IEEE International Solid-State Circuits Conference(ISSCC) Digest of Technical Papers, pp. 338-340, 2016. [12] Jeffrey Chuang, and Harish Krishnaswamy, “A 0.0049〖mm〗^2 2.3GHz Sub-Sampling Ring-Oscillator PLL with Time-Based Loop Filter Achieving -236.2dB Jitter-FOM,” IEEE International Solid-State Circuits Conference(ISSCC) Digest of Technical Papers, pp. 328-329, 2017. [13] Shiheng Yang, Jun Yin, Pui-In Mak, and Rui P. Martins, “A 0.0056〖mm〗^2 All-Digital MDLL Using Edge Re-Extraction, Dual-Ring VCOs and a 0.3mW Block-Sharing Frequency Tracking Loop Achieving 292fs Jitter and -249dB FOM,” IEEE International Solid-State Circuits Conference(ISSCC) Digest of Technical Papers, pp. 118-120, 2018. [14]Behzad Razavi, “Design of Analog CMOS Integrated Circuits” McGraw Hill Education, Second Edition [15] Dongyi Liao, Ruixin Wang, and Fa Foster Dai, “A low-noise inductor-less fractional-N sub-sampling PLL with multi-ring Oscillator”, IEEE Radio Frequency Integrated Circuits Symposium, pp. 108-111, June, 2017. [16] Che-Fu Liang, and Ping-Ying Wang, “A Wideband Fractional-N Ring PLL Using a Near-Ground Pre-Distorted Switched-Capacitor Loop Filter”, IEEE International Solid-State Circuits Conference(ISSCC) Digest of Technical Papers, pp. 190-192, 2015. [17] Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, and Ken Chang, “A Pulse-Position-Modulation Phase-Noise-Reduction Techniques for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS”, IEEE International Solid-State Circuits Conference(ISSCC) Digest of Technical Papers, pp. 52-54, 2014. [18] Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong-Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, and Pavan Kumar Hanumolu, “A 4.25GHz-4.75GHz Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-mode Phase Interpolator With 13.2dB Phase Noise Improvement” IEEE Symposium in VLSI Circuits Digest of Technical Paper, pp. 230-231, 2014. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/72620 | - |
| dc.description.abstract | 本論文呈獻一個操作於52.5億赫茲，以環形振盪器為基礎之鎖相迴路，具有次取樣內圈相位雜訊濾波器，可以達到較小的抖動。本架構使用雜訊抑制的負回授系統。近年來，許多相位雜訊濾波器都使用壓控延遲線和延遲單元以萃取出雜訊的資訊。但是，這些壓控延遲線和延遲單元電路的雜訊，往往嚴重地影響電路的表現。此外，因為穩定度的緣故，鎖相迴路的頻寬被限制在參考頻率的十分之一。所以，我們提出了具有次取樣內圈相位雜訊濾波器，在此架構中，沒有任何壓控延遲線和延遲單元用來萃取雜訊的資訊。還可以將鎖相迴路的頻寬延伸至參考頻率的三分之一。
此濾波器使用次取樣相位偵測器對鎖相迴路的輸出做取樣，將相位誤差轉換為電壓誤差。並且使用電容來儲存此電壓誤差維持了些許週期。然後，次取樣電流泵將目前週期的電壓誤差與前一個週期電壓誤差做相減。並且產生了一個具有誤差資訊的電流到迴路濾波器以校正輸出相位。 此外，這個架構可以額外地產生出一個在左半平面的零點，因此我們可以將頻寬延伸到參考頻率的三分之一，且沒有任何穩定度的疑慮。藉由此具有次取樣內圈相位雜訊濾波器，不只環形振盪器的雜訊，甚至相位頻率偵測器、電流泵的雜訊都可以被抑制。這個架構執行在40奈米互補式金屬氧化物半導體的製程，在0.9伏特的電源供應下，消耗9.01毫瓦。鎖相迴路輸出方均根抖動從50千赫茲積分至10百萬赫茲為1.95 微微秒。 | zh_TW |
| dc.description.abstract | This thesis presents a 5.25-GHz ring-oscillator (RO)-based PLL that achieves low jitter by using a sub-sampling inner-loop phase noise filter (PNF). A feedback noise cancellation is utilized. Recently, voltage-controlled delay lines (VCDLs) and delay cells are widely used to extract the error information in PNFs. However, the noise of VCDLs or delay cells always limits the performance significantly. In addition, PLL bandwidth is limited to one-tenth of the reference frequency for the stability consideration. As a result, we proposed a sub-sampling inner-loop PNF without any VCDLs and delay cells to extract error information, and the bandwidth of this work is also extended to about one-third of reference frequency.
It samples the PLL output, to obtain an error voltage corresponding to phase error by SSPD. Capacitors are used to hold the voltage error for some period of time. Then, SSCP compares the error of the current period with the previous periods’. Then, it produces a current, which is proportional to the error information, to loop filter (LPF) in order to calibrate the output phase. Besides, this structure can produce an additional zero which is on the left-half plane, so the bandwidth can be extended to about one-third of reference frequency without the stability problem. By using a sub-sampling inner-loop PNF, not only VCO noise but also PFD/CP can be eliminated. Implemented in a 40-nm CMOS technology, it consumes 9.01 mW from a 0.9-V supply. The RMS PLL output jitter integrated from 50 kHz to 10 MHz is 1.95ps. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T07:02:05Z (GMT). No. of bitstreams: 1 ntu-108-R05943025-1.pdf: 7120278 bytes, checksum: ddc675182393828004fc053126e822c2 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 ii Abstract iii Contents iv List of Figures vi List of Tables x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Basic Concept 3 2.1 Background 3 2.2 Review of First tape out 8 2.3 Review of the sub-sampling PLL 18 2.4 Summary 20 Chapter 3 Proposed Structure of PLL with a Sub-Sampling Inner-Loop PNF 21 3.1 Proposed Structure 21 3.2 Nosie Consideration and The Stability Analysis 27 3.3 Research purpose and advantages of the proposed structure 33 3.4 Challenges of the proposed structure 34 3.5 Summary 35 Chapter 4 Circuit Implementation 37 4.1 Sub-sampling phase detector (SSPD) 37 4.2 Sub-sampling Charge Pump (SSCP) 44 4.3 Voltage-Controlled Oscillator (VCO) 46 4.4 Voltage-Controlled Delay Line (VCDL) 48 4.5 Charge Pump (CP) 50 4.6 Digital Circuits 52 4.7 Input/Output Buffer 55 4.8 Summary 58 Chapter 5 Simulation Results 59 5.1 Open-Loop simulation 59 5.2 Behavioral simulation 64 5.3 System simulation 65 5.4 Phase noise analysis 68 5.5 Summary 70 Chapter 6 Experimental Results 73 6.1 Print Circuit Board Design 73 6.2 Measurement Environment 75 6.3 Area and Power Dissipation 76 6.4 Measurement Results 77 6.5 Comparison 85 6.6 Summary 85 Chapter 7 Conclusion 87 Reference 89 Biography 91 | |
| dc.language.iso | en | |
| dc.title | 具有次取樣內圈相位雜訊濾波器之鎖相迴路設計 | zh_TW |
| dc.title | The Design and Analysis of a Phase-Locked Loop with a Sub-Sampling Inner-Loop Phase Noise Filter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),林宗賢(Tsung-Hsien Lin),鄭國興(Kuo-Hsing Cheng),彭永州(Yong-Chou Peng) | |
| dc.subject.keyword | 鎖相迴路,延遲迴路,次取樣相位偵測器,雜訊抑制,相位雜訊濾波器, | zh_TW |
| dc.subject.keyword | phase-locked loop (PLL),delay-locked loop (DLL),sub-sampling phase detector (SSPD),noise cancellation,phase noise filter(PNF), | en |
| dc.relation.page | 91 | |
| dc.identifier.doi | 10.6342/NTU201901240 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-07-31 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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