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DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 李建模(Chien-Mo Li) | |
dc.contributor.author | Yi-Zhan Hsieh | en |
dc.contributor.author | 謝宜展 | zh_TW |
dc.date.accessioned | 2021-06-17T06:28:08Z | - |
dc.date.available | 2020-09-29 | |
dc.date.copyright | 2020-09-29 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-09-20 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/72193 | - |
dc.description.abstract | 現行有許多人工智慧與物聯網結合的例子。然而,機器學習需要大量運算,而物聯網裝置通常又會有功耗的限制。因此,如何讓物聯網裝置本身就能夠處理機器學習是一個很有挑戰的項目。脈衝神經網路使用脈衝訊號作為傳輸資訊的方式,而且脈衝神經網路在硬體上的實作會比現行主流的神經網路在硬體上實作要來得省電。然而,也因為脈衝神經網路本身隨機特性以及容錯能力,針對脈衝神經網路晶片的測試難度非常高。在本篇論文中,我們提出七個有關脈衝神經網路的錯誤模型,這些模型都是基於脈衝神經網路中的神經元以及突觸的運作方式做為發想。另外我們也提出專門測試脈衝神經網路晶片的測試流程。這個測試流程會把晶片的輸出當作一個分布來處理,而不像傳統測試方法當作一組特定的值。實驗結果說明雖然神經網路本身具有容錯能力,還是有兩個錯誤模型對脈衝神經網路晶片有很大的影響。針對手寫數字辨識用途的晶片,在錯誤模擬的實驗中,通過我們的測試流程的晶片具有88.90%的準確率。在考慮隨機因素的情況下,這樣的準確率與正常的晶片相同。 | zh_TW |
dc.description.abstract | Nowadays, there are many IoTs integrated with AI. However, machine learning needs intensive computation, which leads to high power consumption. It is a challenge to perform machine learning on IoT devices locally. Spiking neural network (SNN) is a very promising low power neural network that can be implemented in asynchronous circuits. However, it is hard to test SNN chips since it is inherently probabilistic and fault tolerant. So far, there is no good fault model and test method suitable for SNN chips. In this work, we propose seven behavior fault models for SNN based on the function of neurons and synapses. We also propose a test method, which considers the output response as a distribution rather than specific values. The experiment results on a MNIST dataset show that although SNN is fault tolerant, two fault models are still critical for SNN chips. Given a specific application, the accuracy of chips that passed our test is 88.90%, which is indistinguishable from that of good chips, considering the effects of random seeds. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T06:28:08Z (GMT). No. of bitstreams: 1 U0001-1909202016053200.pdf: 2694449 bytes, checksum: 2823071e2ad4d2aa814b024d36204143 (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 致謝 ii 摘要 iii Abstract iv Table of Contents v List of Figures vii List of Tables viii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Techniques 5 1.3 Contributions 5 1.4 Organization 6 Chapter 2 Background 7 2.1 Spiking Neural Network (SNN) 7 2.2 Suitable HW Implementation for SNN 12 2.3 Related Work 13 Chapter 3 Proposed Fault Model 15 3.1 Spike Faults 15 3.2 Weight Fault 18 3.3 Delay Faults 19 3.4 Connectivity Faults 20 3.5 Scalability of Fault Models 21 Chapter 4 Testing SNN Chips 22 4.1 Test Method 22 4.2 SNN Chip Simulator 23 4.3 Hypothesis Test and Pass/Fail Criterion 24 4.4 F1 Score 25 Chapter 5 Experimental Result 28 5.1 Experiment Setting 28 5.2 Impact on Accuracy 31 5.3 Fault Testing 32 5.4 Test Method Evaluation 34 Chapter 6 Discussion 39 6.1 Fault Sampling 39 6.2 Number of Simulations 40 Chapter 7 Conclusion 43 Acknowledgements 44 References 44 | |
dc.language.iso | en | |
dc.title | 脈衝神經網路晶片之錯誤模型以及測試 | zh_TW |
dc.title | Fault Modeling and Testing of Spiking Neural Network Chips | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),劉宗德(Tsung-Te Liu) | |
dc.subject.keyword | 脈衝神經網路,積體電路測試,錯誤模型,錯誤模擬, | zh_TW |
dc.subject.keyword | Spiking Neural Network,VLSI testing,Fault modeling,Fault simulation, | en |
dc.relation.page | 48 | |
dc.identifier.doi | 10.6342/NTU202004219 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2020-09-22 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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