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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂良鴻(Liang-Hung Lu) | |
| dc.contributor.author | Kai-Han Cheng | en |
| dc.contributor.author | 鄭楷翰 | zh_TW |
| dc.date.accessioned | 2021-06-17T06:14:03Z | - |
| dc.date.available | 2023-10-02 | |
| dc.date.copyright | 2018-10-02 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-09-25 | |
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Pun, 'A high-linearity capacitance-to-digital converter suppressing charge error from bottom-plate switches,' IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 41, no. 7, pp. 1928-1941, Jul. 2014. [19] S. Oh, W. Jung, K. Yang, D. Blaauw, and D. Sylvester, '15.4b Incremental Sigma-Delta Capacitance-to-Digital Converter with Zoom-in 9b Asynchronous SAR,' in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014. [20] S. Oh et al., 'A dual-slope capacitance-to-digital converter integrated in an implantable pressure-sensing system,' IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1581-1591, Jul. 2015. [21] W. Jung, S. Jeong, S. Oh, D. Sylvester, and D. Blaauw, 'A 0.7pF-to-10nF fully digital capacitance-to-digital converter using iterative delay-chain discharge,' in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015. [22] H. Danneels, K. Coddens, and G. Gielen, 'A fully-digital, 0.3 V, 270 nW capacitive sensor interface without external references,' in IEEE Proc. ESSCIRC, Sep. 2011. [23] J. H.-L. Lu , M. Inerowicz , S. Joo , J. K. Kwon and B. Jung, 'A low-power, wide-dynamic-range semi-digital universal sensor readout circuit using pulse width modulation', IEEE Sensors J., vol. 11, pp. 1134-1144, 2011. [24] Z. Tan, R. Daamen, A. Humbert, Y. Ponomarev, Y. Chae and M. Pertijs, 'A 1.2-V 8.3-nJ CMOS humidity sensor for RFID applications', IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2469-2477, 2013. [25] H. Ha, D. Sylvester, D. Blaauw and J. Sim, 'A 160 nW 63.9 fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes', IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 220-221. [26] Y. He, Z. Chang, L. Pakula, S.-H Shalmany and M. Pertijs, ' A 0.05mm2 1V capacitance-to-digital converter based on period modulation', IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 486-487. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71898 | - |
| dc.description.abstract | 近年來，隨著互補式金屬氧化物半導體製程的不斷演進，下降的操作電壓使得類比電路的設計面臨更大的挑戰。從而，將訊號在時域上進行操作提供了一個可能的方向去解決問題。因此本論文使用了數種時域訊號處理的技巧，使用90奈米互補式金氧半製程來實做高能源效率的三角積分資料轉換器。首先，此研究透過免閘式環型震盪器來實現一個二階三角積分時間至數位轉換器，操作在 1.0 伏特的情況下，晶片功耗為 330 微瓦，並且在1 MHz的頻寬內有 11.3 位元的解析度，達到 0.25 pJ/c.-s. 的品質因數。進一步的，透過一個高線性度的電容至時間轉換電路來將時間至數位轉換器應用至電容感測介面電路，操作在 0.6 伏特的情況下，晶片功耗為 6.77 微瓦，此電路的輸入電容範圍為8皮法拉，並且在2 kHz的頻寬內有 11.2 位元的解析度，達到0.72 pJ/c.-s.的品質因數。 | zh_TW |
| dc.description.abstract | In recent years, as CMOS technology continues to advance, design of traditional analog circuits becomes more challenging due to the lower operation voltage. Thus, operating signals in time-domain paves a possible way to alleviate the problem. This thesis utilizes several time-mode signal processing techniques for energy efficient delta-sigma data converters. Fabricated in a 90-nm CMOS process, a second-order delta-sigma time-to-digital converter (TDC) which consumes 330 μW from a 1.0-V supply is realized with gated-free ring oscillators. This design demonstrates a resolution of 11.3 bits within 1-MHz signal bandwidth and achieves an FoM of 0.25 pJ/c.-s. Furthermore, a capacitance-to-digital converter (CDC) composed of a highly linear capacitance-to-time circuit and the proposed TDC is implemented. Consuming 6.77 μW from a 0.6-V supply, the CDC demonstrates a resolution of 11.2 bits in 2-kHz signal bandwidth. This design achieves an FoM of 0.72 pJ/c.-s. for an input capacitance range of 8 pF. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T06:14:03Z (GMT). No. of bitstreams: 1 ntu-107-R05943120-1.pdf: 2036503 bytes, checksum: dca2e0c6c94dba8bb095237dc7e51da8 (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 致謝 i
摘要 iii Abstract v Contents vii List of Figures x List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Background 3 2.1 Applications 3 2.2 Performance metrics of TDC 5 2.2.1 Static performance 5 2.2.2 Dynamic performance 7 2.2.3 Counting rate and dead time 8 2.3 General TDC architecture 9 2.4 Delta-sigma TDC 14 Chapter 3 A Second-Order Delta-Sigma Time-to-Digital Converter Based on Gated-Free Ring Oscillators 23 3.1 Overview 23 3.2 Conventional gated ring oscillator TDC 24 3.3 Proposed delta-sigma TDC 26 3.4 Circuit implementation 29 3.4.1 Time register 29 3.4.2 Leakage suppression switches 31 3.4.3 Gated-free ring oscillator 32 3.4.4 Sequential search frequency calibration 34 3.4.5 Counters 36 3.5 Noise analysis 37 3.5.1 Quantization noise 37 3.5.2 Thermal noise 37 3.5.3 Estimated signal-to-noise ratio 38 3.6 Measurement results 39 3.7 Summary 46 Chapter 4 A Time-Mode Capacitive Sensor Interface with Second-Order Delta-Sigma Time-to-Digital Converter 47 4.1 Overview 47 4.2 Proposed capacitance-to-digital converter 49 4.2.1 Conventional capacitance-to-time circuit 49 4.2.2 Proposed capacitance-to-time circuit 52 4.3 Circuit implementation 54 4.3.1 Capacitance-to-time circuit 54 4.3.2 Time-to-digital converter 55 4.4 Noise analysis 56 4.4.1 Quantization noise 56 4.4.2 Thermal noise 57 4.4.3 Estimated signal-to-noise ratio 57 4.5 Measurement results 58 4.6 Summary 63 Chapter 5 Conclusion 65 References 67 | |
| dc.language.iso | en | |
| dc.subject | 三角積分 | zh_TW |
| dc.subject | 介面電路 | zh_TW |
| dc.subject | 時間數位轉換器 | zh_TW |
| dc.subject | 電容數位轉換器 | zh_TW |
| dc.subject | delta sigma | en |
| dc.subject | TDC | en |
| dc.subject | sensor interface | en |
| dc.subject | CDC | en |
| dc.title | 應用於電容感測之高能效三角積分時間數位轉換器 | zh_TW |
| dc.title | Energy Efficient Delta-Sigma Time-to-Digital Converters for Capacitive Sensing Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),黃俊郎(Jiun-Lang Huang),郭建男(Chien-Nan Kuo) | |
| dc.subject.keyword | 三角積分,時間數位轉換器,介面電路,電容數位轉換器, | zh_TW |
| dc.subject.keyword | delta sigma,TDC,sensor interface,CDC, | en |
| dc.relation.page | 71 | |
| dc.identifier.doi | 10.6342/NTU201804135 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-09-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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