請用此 Handle URI 來引用此文件:
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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 李建模(Chien-Mo Li) | |
dc.contributor.author | Yen-Ting Kuo | en |
dc.contributor.author | 郭彥庭 | zh_TW |
dc.date.accessioned | 2021-06-17T06:10:49Z | - |
dc.date.available | 2020-11-13 | |
dc.date.copyright | 2020-11-13 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-10-19 | |
dc.identifier.citation | Yongchan Ban, Yongseok Kang, and Woohyun Paik, 'Model-based CMP (Chemical-Mechanical Polishing) proximity correction for mitigating systematic process variations,' 2015 International SoC Design Conference (ISOCC). IEEE, 2015. Shekhar Borkar, et al., 'Parameter variations and impact on circuits and microarchitecture,' Proceedings of the 40th annual Design Automation Conference. 2003. Shekhar Borkar,'Designing reliable systems from unreliable components: the challenges of transistor variability and degradation,' IEEE Micro 25.6 (2005): 10-16. Keng-Wei Chang, et al., 'DVFS Binning Using Machine-Learning Techniques,' IEEE International Test Conference in Asia (ITC-Asia), 2018. Janine Chen, et al. 'Data learning techniques and methodology for Fmax prediction,' 2009 IEEE International Test Conference, 2009. Janine Chen, et al., 'Selecting the most relevant structural Fmax for system Fmax correlation,' 2010 28th VLSI Test Symposium (VTS). IEEE, 2010. A. T. Fiory, 'Rapid thermal processing for silicon nanoelectronics applications,' The Journal of The Minerals 57.6 (2005): 21-26. Anne Gattiker, 'Unraveling variability for process/product improvement,' 2008 IEEE International Test Conference, 2008. Alexander Gepperth, and Barbara Hammer, 'Incremental learning algorithms and applications,' 2016. Lei He, et al., 'Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization,' Design and Process Integration for Microelectronic Manufacturing III. Vol. 5756. International Society for Optics and Photonics, 2005. Jungran Lee, et al., 'IC performance prediction for test cost reduction,' In IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No. 99CH36314) (pp. 111-114), 1999. Peter Maxwell, Ismed Hartanto, and Lee Bentz, 'Comparing functional and structural tests,' Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159). IEEE, 2000. Szu-Pang Mu, et al., 'Statistical methodology to identify optimal placement of on-chip process monitors for predicting Fmax,' In ACM Proceedings of the 35th International Conference on Computer-Aided Design, 2016. Fabian Pedregosa, et al., 'Scikit-learn: Machine learning in Python,' The Journal of Machine Learning Research 12 (2011): 2825-2830. Adel S. Sedra, et al., Microelectronic circuits, New York: Oxford University Press, 1998. Qihang Shi, et al., 'On-chip sensor selection for effective speed-binning,' Analog Integrated Circuits and Signal Processing 88.2: 369-382, 2016. Joseph M. Steigerwald, Shyam P. Murarka, and Ronald J. Gutmann, Chemical mechanical planarization of microelectronic materials, John Wiley Sons, 1997. Min-Yan Su, 'Chip Performance Prediction Using Machine Learning Techniques,' Master thesis, Graduate Institute of Electronics Engineering, National Taiwan University, 2019 Osman S. Unsal, et al., 'Impact of parameter variations on circuits and microarchitecture,' IEEE Micro 26.6 (2006): 30-39. Hongbo Zhang, et al., 'Characterization of the performance variation for regular standard cell with process nonidealities,' Design for Manufacturability through Design-Process Integration V. Vol. 7974. International Society for Optics and Photonics, 2011. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71816 | - |
dc.description.abstract | 隨著技術的縮減,工藝變化對晶片效能的影響越來越大。 因此,我們需要透過昂貴的功能測試來測試所有的生產晶片。 為了降低測試成本,在這篇論文中,我們提出了一種新的方法來預測生產晶片的最小工作電壓(Vmin)。 此外我們提出了兩個新的關鍵特徵以提高預測準確性。 我們提出的累積學習法可以減少批貨之間差異的影響。 兩個7奈米工業製程設計(大約有120萬顆量產晶片,這些晶片來自142批貨)的實驗結果表明,我們的預測準確度分別為93.4%和89.8%。 我們可以達到95%以上良好的預測(良好的預測意味著在誤差範圍內,預測的最小工作電壓不低於實際最小工作電壓)。 與傳統測試相比,我們的方法可以節省75%的測試時間。 要實施此方法,我們需要針對初始訓練和累積訓練分別設置測試流程。 | zh_TW |
dc.description.abstract | As technology scales down, process variations have an increasing impact on chip performance. Therefore, we need to test all production chips by expensive functional test. For test cost reduction, in this thesis, we propose a new methodology to predict minimum operating voltage (Vmin) for production chips. In addition, we propose two new key features to improve the prediction accuracy. Our proposed accumulative learning can reduce the impact of lot-to-lot variations. Experimental results on two 7nm industry designs (about 1.2M production chips from 142 lots) show that our prediction accuracies are 93.4% and 89.8%, respectively. We can achieve above 95% good prediction (good prediction means that the predicted Vmin is no lower than the actual Vmin within an error bound). Our methodology can save 75% test time compared with traditional testing. To implement this method, we will need to have separate test flow for the initial training and accumulative training. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T06:10:49Z (GMT). No. of bitstreams: 1 U0001-1910202011325600.pdf: 2707844 bytes, checksum: 1d820bddcf0b2d7c241ec88519cda56f (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 致謝 i 中文摘要 iii ABSTRACT iv CONTENTS v LIST OF FIGURES vi LIST OF TABLES vii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Techniques 5 1.3 Contributions 6 1.4 Organization 7 Chapter 2 Background 8 2.1 Parameter Variations 8 2.2 Chemical-mechanical Polishing 12 2.3 Previous Work 14 2.4 Our Advantages Over Previous Work 19 Chapter 3 Proposed Techniques 20 3.1 Overall Flow 20 3.2 Feature Extraction 22 3.3 Initial Learning 25 3.4 Accumulative Learning 27 Chapter 4 Experimental Results 29 4.1 Experimental Setup 29 4.2 Lot-to-lot Variation 29 4.3 Comparison of Features 32 4.4 Comparison of Models 35 4.5 Test Time Comparison 39 Chapter 5 Discussion 40 5.1 What If Validation Fail ? 41 5.2 Wafer Test Data vs Package Test Data 42 5.3 Speed Binning 43 5.4 Future Work 45 Chapter 6 Conclusion 46 References 47 | |
dc.language.iso | en | |
dc.title | 使用累積學習預測生產測試中晶片的最小工作電壓 | zh_TW |
dc.title | Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 方家偉(Jia-Wei Fang),江蕙如(Hui-Ru Jiang) | |
dc.subject.keyword | 製程變異,機器學習,晶片效能預測, | zh_TW |
dc.subject.keyword | Process variation,Machine Learning,Chip Performance Prediction, | en |
dc.relation.page | 49 | |
dc.identifier.doi | 10.6342/NTU202004287 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2020-10-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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