請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71556
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳怡然(Yi-Jan Chen) | |
dc.contributor.author | Yang-An Lin | en |
dc.contributor.author | 林洋安 | zh_TW |
dc.date.accessioned | 2021-06-17T06:03:11Z | - |
dc.date.available | 2022-01-29 | |
dc.date.copyright | 2019-01-29 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2019-01-28 | |
dc.identifier.citation | [1] A. Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters,” in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), Sept. 1999, pp. 1193 – 1196.
[2] G. Van der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, and G. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE J. Solid-State Circuits, vol. 34, pp. 1708–11 718, Dec. 1999. [3] J. Deveugele, G. Van der Plas, M. Steyaert, G. Gielen, W. Sansen, “A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC”, IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 51, Issue 1, pp:191-195, Jan. 2004. [4] A. Van der Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 12 b 500 Msample/S current-steering CMOS D/A,” in Proc. Int. Solid-State Circuits Conf. (ISSCC) , 2001, pp. 366–367. [5] J. Deveugele and M. S. J. Steyaert , “A 10b 250MS/s binary-weighted current-steering DAC,” IEEE J. Solid-State Circuits, vol.41, no.2, pp.320-329, Feb.2006. [6] W. T. Lin and T.-H. Kuo, 'A 12b 1.6GS/s 40mW DAC in 40nm CMOS with > 70dB SFDR over entire Nyquist bandwidth,' in Solid State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 474-475. [7] A. R. Bugeja and B.-S. Song, “A self-trimming 14-b 100-MS/s CMOS DAC,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1841–1852, Dec. 2000. [8] M-J. Choe, “Return-to-zero current switching digital-to-analog converter,” U.S. Patent 7042379B2, May 2006. [9] S. Park, G. Kim, S. Park and W. Kim, “A digital-to-analog converter based on differential-quad switching,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1335-1938, Oct. 2002. [10] E. Olieman, A. -J. Annema,and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits, vol. 50, no. 3, March 2015. [11] A. Van den Bosch et al., “A 10-bit 1-GSample/s nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315-324, Mar.2001 [12] Jung, J. , Baek, K. H. , Lim, S. I. , Kim, S. , Kang, S. M. , “Design of a 6 bit 1.25 GS/s DAC for WPAN,” Proc. 2008 Int. Symp. Circuits and Systems, May 2008, pp. 2262–2265. [13] Y. Zhou and J. Yuan, “An 8-bit 100-MHz CMOS linear interpolation DAC,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1109-1113, Nov. 2008. [14] L. R. Carley, “A noise-shaping coder topology for 15+ bit converters,” IEEE J. Solid-State Circuits, vol. 28, pp. 267–273, Apr. 1989. [15] W. –T . Lin and T.-H. Kuo, “A compact dynamic-performance-improved current-steering DAC with random rotation-based binary-weighted selection,” IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 444-453, Feb. 2012. [16] K. O’Sullivan, C. Gorman, M. Hennessy, and V. Callaghan, “A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm2,” IEEE J. Solid-State Circuits, vol. 39, pp. 1064-1072, July 2004. [17] A. R. Bugeja, B. S. Song, P.L. Rakers, S.F. Gillig, “A 14-b, 100MS/s CMOS DAC designed for spectral performance”, IEEE J. Solid State Circuits, vol. 34, pp. 1719–1732, 1999. [18] H. C. Yang, T. S. Fiez, and D. J. Allstot, “Current-feedthrough effects and cancellation techniques in switched-current circuits,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 3186-3189, 1999. [19] M. J. Pelgrom et al., “Matching properties of mos transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433–1439, 1989. [20] D. Seo, G. H. McAllister, “A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for baseband wireless transmitter,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 486-495, Mar. 2007. [21] Behzad Razavi, “Design of analog CMOS integrated circuits”. [22] S. Luscgas, R. Schreier and Hae-Seung Lee, “ Radio frequency digital-to-analog converter,” IEEE J. Solid-State Circuits, vol.39, no.9, pp.1462-1467, Sept. 2004 [23] S. Balasubramanian and W. Khalil, “Direct digital-to-RF digital-to-analogue converter using image replica and nonlinearity cancelling architecture,” IET Electronics Letters, vol. 46, no. 14, pp. 1030-1032, Jul. 2010. [24] E. Olieman, A. -J. Annema, B. Nauta, A. Bal, and P.N. Singh, “A 12b 1.7 GS/s two-times interleaved DAC with < -62 dBc IM3 across nyquist using a single 1.2 V supply,” in 2013 IEEE Asian Solid-State Circuits Conf.(A-SSCC), Singapore, pp. 81-84, Nov. 2013. [25] F. T. Chou and C. C. Hung. ,”Glitch energy reduction and SFDR enhancement techniques for low-power binary-weighted current-steering DAC,” IEEE Trandsctions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, June. 2016. [26] G. Engel, S. Kuo, and S. Rose, “ A 14b 3/6 GHz current-steering RF DAC in 0.18μm CMOS with 66 dB ACLR at 2.9 GHz,” in 2012 IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 458-460. [27] D. G. Manolakis , V. K. Ingle, “Applied digital signal processing ”. [28] R. G. Lyins, “ Understanding digital signal processing 2nd Edition ”. [29] W. H. Tseng, J. T. Wu, and Y. C. Chu, 'A CMOS 8-bit 1.6-GS/s DAC with digital random return-to-zero,' IEEE Transactions on Circuits and Systems II-Express Briefs, vol. 58, pp. 1-5, Jan 2011. [30] K. Hausmair, S. Chi, P. Singerl, and C. Vogel, “Aliasing-free digital pulse-width modulation for burst-mode RF transmitters,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 60, no. 2, pp. 415-427, Feb. 2013. [31] S. N. Kim, W. C. Kim , M- . J. Seo, and S- . T. Ryu “A 65-nm CMOS 6-Bit 20GS/s Time-Interleaved DAC with Full binary sub DACs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 9, pp. 1154–1158,Sep. 2018 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71556 | - |
dc.description.abstract | 本論文主旨為實現一具備四倍內插升頻之數位類比轉換器,為了讓數位類比轉換器能夠操作在高速,本論文所採之架構為電流引導式之數位類比轉換器,在訊號輸入數位類比轉換器前,將先經過一具有升頻功能之數位合成的內插升頻電路,不僅可以增加輸出結果的取樣點數,讓電壓輸出波型更加柔和,更能利用內插的特性在以取樣頻率為中心點的兩端產生輸入頻率之諧波,進而達到將所輸入之頻譜升頻至取樣頻率的功能。最後在佈局圖的部分利用分散電流源的方式來減少電流源的不匹配效應(Mismatch)。
在晶片實現上,均使用0.13微米CMOS實現電路,整體晶片面積為0.9 × 0.9 〖mm〗^2,其中電流源電路的面積為 0.584 × 0.665 〖mm〗^2,並在電源電壓1.2 V下達到差動輸出擺幅為0.8 V的數位類比轉換器,根據量測結果,INL/DNL皆小於0.3 LSB,SFDR約為38 dB左右,而總功率消耗約為23 mW。在AFDPWM訊號應用方面,量測K值為3,PWM頻率為15 MHz,頻寬為3MHz的狀況下,ACLR量測出來的結果為-29.2 dBc,將訊號載波至中心頻為40 MHz時,ACLR則為 -28.9 dBc左右。 | zh_TW |
dc.description.abstract | The purpose of this thesis is to implement a digital-to-analog converter with four times up-sampling technique by using interpolation. To make the digital-to-analog converter operate in high frequency, the architecture adopted is current-steering method. Before the input signal goes into the digital-to-analog converter, it will first pass through the digital-synthesis circuit with interpolative up-sampling function. This interpolative up-sampling circuit not only improves the linearity of the output, but also generates harmonics centered at the up-sampling carrier frequency and make the input signal up-sampled to the carrier frequency by its interpolative characteristic, which is the main goal of this thesis. In the layout part, this thesis splits the current source placement to reduce the mismatch of the current sources.
The chip designed in this thesis is implemented in 0.13μm CMOS process. The chip size is 0.9×0.9 m'm' ^'2' and the size of current source part is 0.584×0.665 m'm' ^'2' . The output swing is 0.8 V by using 1.2 V supply voltage. The measured DNL/INL are both less than 0.3 LSB, SFDR is 38 dB with 10 MHz sine wave and the total power consumption is 23 mW. In the AFDPWM (aliasing-free digital pulse width modulation ) application , the measured ACLR is -29.2 dBc when K factor is 3, frequency of PWM is 15 MHz and the bandwidth is 3 MHz, and the measured ACLR is -28.9 dBc when the signal is up-convert to 40 MHz. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T06:03:11Z (GMT). No. of bitstreams: 1 ntu-107-R04943128-1.pdf: 4596064 bytes, checksum: 2e049f240fa620dbf99054957c3eae3b (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | 口試委員審定書………………………………………………………………………1
中文摘要 .......................................................................................................................i Abstract .........................................................................................................................ii 目錄 ............................................................................................................................iii 圖目錄 ........................................................................................................................v 表目錄 ........................................................................................................................ix Chapter 1 緒論…………………………………..………………………...………..1 1.1 研究動機 …………………………………………………………....…….1 1.2 文獻回顧………………………………………………………………..….2 Chapter 2 數位類比轉換器簡介 ……………………...…………………………..8 2.1 簡介……………………………………………………………………..….8 2.2 理想數位類比轉換器……………………………………………………...8 2.3 數位類比轉換器靜態參數…………………………………………….....10 2.4 數位類比轉換器傳輸及動態參數…………………………………….....14 Chapter 3 數位類比轉換器基本架構 …………………………………..…….....18 3.1 電阻式數位類比轉換器……………………………………………….....18 3.2 二進位碼數位類比轉換器…………………………………………….....19 3.3 電容電荷重新分配式數位類比轉換器……………………………….....22 3.4 電流切換式數位類比轉換器………………………………………...…..24 Chapter 4 數位類比轉換器設計考量….…………………………………………28 4.1 電流源負載效應 …………………………………………..………….…28 4.2 切換瞬變效應 …………………………………………………………...32 4.2.1 差動開關對同時關閉 ………………………………………………..34 4.2.2 時鐘饋通效應及電荷注入效應 ……………………………………..35 4.2.3 時鐘偏移 ……………………………………………………………..36 4.3 電晶體不匹配 …………………………………………………………...36 4.4 佈局圖不匹配 …………………………………………………………...37 Chapter 5 內插升頻器設計考量 ………………………………………………….38 5.1 Nyquist-rate theorem ………………………………………………….…...38 5.2 Upsampling theorem ………………………………………………….……39 5.3 Interpolation theorem ……………………………………………………...41 Chapter 6 電路設計及模擬 ……………………………………………………….45 6.1 電流架構與規格 ……………………………………………………….....45 6.2 電流源電路 ……………………………………………………………….46 6.3 門栓及緩衝電路 ………………………………………………………….51 6.4 電流源偏壓電路 ………………………………………………………….55 6.5 內插升頻電路 …………………………………………………………….55 6.6 數位類比轉換器整體模擬結果 ………………………………………….59 Chapter 7 模擬及量測結果 ……………………………………………………….65 7.1 模擬結果 ……………………………………………………………..…….65 7.2 印刷電路板(PCB)與量測佈置 ….....………...…………...………..………72 7.3 量測結果 …………………………………………………..……………….77 Chapter 8 AFDPWM應用 ………………………………………………………...81 Chapter 9 參考文獻 ……………………………………………………………….88 | |
dc.language.iso | zh-TW | |
dc.title | 0.13 µm CMOS 內插升頻式數位類比轉換器 | zh_TW |
dc.title | 0.13 µm CMOS Digital to Analog Converter with Upsampling Interpolation Technique | en |
dc.type | Thesis | |
dc.date.schoolyear | 107-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),余帝榖(Ti-Ku Yu),陳昭宏(Jau-Horng Chen) | |
dc.subject.keyword | 電流式數位類比轉換器,內插升頻技術, | zh_TW |
dc.subject.keyword | Current-Steering D/A converter,Interpolation up-sampling technique, | en |
dc.relation.page | 92 | |
dc.identifier.doi | 10.6342/NTU201900225 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2019-01-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-107-1.pdf 目前未授權公開取用 | 4.49 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。