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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | You-Rong Qiu | en |
dc.contributor.author | 邱宥榮 | zh_TW |
dc.date.accessioned | 2021-06-17T06:02:59Z | - |
dc.date.available | 2022-01-30 | |
dc.date.copyright | 2019-01-30 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-01-28 | |
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Tae-Kwang Jang, Xing Nan, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun Kim, Taeik Kim, Jaejin Park, Hojin Park, “A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter”, IEEE ISSCC Dig. Tech. Papers Feb. 2013, pp.254-255. J Chun-Wei Hsu, Karthik Tripurari, Shih-An Yu, Peter R. Kinget, “A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference”, IEEE J. Solid-State Circuits, vol. 44, pp. 3253–3263, December 2015. Kenta Sogo, Akihiro Toya and Takamaro Kikkawa, “A Ring-VCO-Based Sub-Sampling PLL CMOS Circuit with -119 dBc/Hz Phase Noise and 0.73 ps Jitter”, Proc. IEEE European Solid-State Circuit Conference, pp. 253-256, 2012. Brian Drost, Member, IEEE, Mrunmay Talegaonkar and Pavan Kumar Hanumolu, “A Analog Filter Design Using Ring Oscillator Integrators”, IEEE J. Solid-State Circuits, vol. 47, pp. 3120–3129, December 2012. Mark Ferriss, Jean-Olivier Plouchart Arun Natarajan, Alexander Rylyakov,Ben Parker, José A. Tierno, A. Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, andDaniel J. Friedman, “An Integral Path Self-Calibration Scheme for a Dual-Loop PLL”, IEEE J. Solid-State Circuits, vol. 48, pp. 996–1008, April 2013. Jri Lee, and Huaide Wang, “Study of Subharmonically Injection-Locked PLLs ”, IEEE J. Solid-State Circuits, vol. 44, pp. 1539–1553, May 2009. Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, and Luca Selmi, “Modeling, Design and Characterization of a New Low-Jitter Analog Dual Tuning LC-VCO PLL Architecture”, IEEE J. Solid-State Circuits, vol. 40, pp. 1303-1309, June 2005. Salvatore Levantino, Giovanni Marzin, Carlo Samori, and Andrea L. Lacaita, “A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration”, IEEE J. Solid-State Circuits, vol. 48, pp. 2419-2429, October 2013. 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Perrott, “A Low-Noise Wide-BW 3.6-GHz Digital ∆∑ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation”, IEEE J. Solid-State Circuits, vol. 43, pp. 2776-2786, December 2008. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Boston: McGraw-Hill, 2001. Behzad Razavi, RF Microelectronics, Second Edition, Upper Saddle River, NJ: Prentice-Hall, 2012. Behzad Razavi, Design of Integrated Circuit for Optical Communications, New York: McGraw-Hill, 2002. Jri Lee, Communication Integrated Circuits, Jri Lee’s Website, 2018. 劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71548 | - |
dc.description.abstract | 本論文為一個小面積之鎖相迴路並採用次取樣與突波降低技術。現今中央處理器採用多個鎖相迴路分別給不同核心單元獨立使用,針對不同核心的工作狀態,動態地調整時脈頻率來減少功率消耗,同時隨著製程的演進,單位面積的製程成本持續成長,因此鎖相迴路的面積必須小型化,並且維持同樣的效能。傳統鎖相迴路中的迴路濾波器是由被動電容所組成,其占了晶片大部分的面積,因此把儲存電荷的電容改為儲存相位之電流控制震盪器可省下大量的面積。為了降低輸出的相位雜訊,本論文採用次取樣技術,當迴路鎖定頻率且參考訊號與除頻器輸出訊號相位差小於180度後,迴路會關閉增益較低的相位/頻率偵測器,改由較高增益的次取樣相位偵測器鎖定相位來降低其他電路所產生的雜訊,同時迴路也會關閉除頻器路徑,使其不會貢獻相位雜訊至系統。然而次取樣技術附帶的非理想效應會讓輸出訊號的參考突波增加,因此採用突波降低技術來減少次取樣電路所帶來的缺點。本晶片使用台積電90奈米互補式金氧半製程,主動區域面積約0.02mm2,在供應電源1.2V下輸出2 GHz頻率,參考突波達到-49.42 dBc,在偏移輸出頻率1MHz的相位雜訊為 -80.32 dBc/Hz,消耗 8.68mW功率。 | zh_TW |
dc.description.abstract | The thesis implements a small area sub-sampling phase-locked loop(PLL) with spur reduction technique. Nowadays, CPUs adopt a number of PLLs for individual core in order to save the power consumption by dynamically adjusting the operation frequency. Along with the progress in process, the cost per unit area keeps increasing. Therefore, the area of PLL needs to be shrunk with the same performance.In the conventional PLL, the loop filter is composed of passive capacitor which occupies the most parts of chip area. As a result, the area of PLL can be saved by replacing the passive capacitor which stores or releases the charges with a current-controlled oscillator and a dummy oscillator which store the phase information. To reduce the output phase noise, the thesis adopts sub-sampling technique. As the output frequency is locked and the phase difference between reference and divider output is less than 180°, the frequency-locked loop is turned off and the sub-sampling phase detector with higher gain dedicates on phase locking. Meanwhile, the divider path is turned off so as to avoid the divider from contributing phase noise to system. However, the sub-sampling technique has three side effects and reference spur is raised up by those disadvantages. Hence, this thesis adopts spur reduction technique to alleviate those disadvantages from sub-sampling technique.This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.02mm^2 and 2GHz operation frequency. The reference spur is -49.42 dBc and phase noise is -80.32 dBc/Hz at 1MHz offset from carrier frequency under 1.2V power supply with 8.68mW power dissipation. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T06:02:59Z (GMT). No. of bitstreams: 1 ntu-108-R05943174-1.pdf: 4022834 bytes, checksum: d20368b22884d3a9fba673258a30ee85 (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 口試委員審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv CONTENTS v LIST OF FIGURES vii LIST OF TABLES x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization 3 Chapter 2 Background 4 2.1 Basic Concepts of PLL 4 2.2 Building Blocks of PLL 5 2.2.1 Phase/Frequency Detector and Charge Pump 5 2.2.2 Loop Filter 8 2.2.3 Voltage-Controlled Oscillator 9 2.2.4 Frequency Divider 11 2.3 The Linear Model for PLL 12 2.3.1 Linear Model of PFD and Charge Pump 13 2.3.2 Linear Model of Loop Filter 13 2.3.3 Linear Model of VCO 15 2.3.4 Linear Model of Frequency Divider 15 2.3.5 Stability Analysis of Phase-Locked Loop 16 2.4 General Design Procedures of Phase-Locked Loop 20 Chapter 3 The Small Area Sub-Sampling PLL with Spur Reduction Technique 22 3.1 Introduction 22 3.2 Architecture 22 3.2.1 Time-Based Integrator 24 3.2.2 Sub-Sampling Phase Detector 27 3.2.3 Spur Reduction Technique 29 3.2.4 System Analysis 33 3.3 Implementation 37 3.3.1 Dead Zone Phase/Frequency Detector and Charge Pump 37 3.3.2 Current-Controlled Ring Oscillator 41 3.3.3 Phase Detector and Charge Pump 45 3.3.4 Sub-Sampling Phase Detector 47 3.3.5 Frequency Divider 49 3.3.6 Timing Control Circuit 50 3.4 Simulation Results 53 Chapter 4 Experimental Results 57 Chapter 5 Conclusion 62 Bibliogrophy 63 | |
dc.language.iso | en | |
dc.title | 一個0.02mm2之鎖相迴路並採用次取樣與突波降低技術實現於90nm CMOS製程 | zh_TW |
dc.title | A 0.02mm2 Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology | en |
dc.type | Thesis | |
dc.date.schoolyear | 107-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 吳安宇(An-Yeu Wu),林宗賢(Tsung-Hsien Lin),陳伯奇(Poki Chen) | |
dc.subject.keyword | 鎖相迴路,電流控制震盪器,小面積,次取樣,突波降低, | zh_TW |
dc.subject.keyword | Phase-locked loop,current-controlled oscillator,small area,sub-sampling,spur reduction, | en |
dc.relation.page | 66 | |
dc.identifier.doi | 10.6342/NTU201900208 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2019-01-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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