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標題: | 應用於LTE-10MHz系統之封包追蹤混合式電源調變器設計 Design of the Envelope Tracking Hybrid Supply Modulator for LTE-10MHz Application |
作者: | Yen-Ting Chen 陳彥廷 |
指導教授: | 林宗賢(Tsung-Hsien Lin) |
關鍵字: | 長期演進技術,封包追蹤,混合式電源調變器,線性放大器,切換式放大器,功率附加效率, Long-Term Evolution,envelope tracking,hybrid supply modulator,linear amplifier,switching amplifier,power-added efficiency, |
出版年 : | 2020 |
學位: | 碩士 |
摘要: | 自長期演進技術開始發展為第四代行動通訊之協定,射頻功率放大器之功率轉換效率便成為射頻發射器設計中愈發嚴重的議題。封包追蹤技術依據輸入封包訊號,調變功率放大器之供應電源,以作為提升其效率的有效解決方案。故相較於給予固定電壓之單一功率放大器,其功率損耗便能明顯降低。
本論文採用混合式電源調變器之架構以實現封包追蹤。此電源調變器包含一個線性放大器以快速追蹤訊號,並提供低輸出阻抗以壓抑雜訊或非線性成份;一個切換式放大器以提供主要的輸出功率,進而達到高功率轉換效率。其中線性放大器包含一個電流再利用之轉導放大器及靜態電流控制之AB類輸出級,且回授路徑加上RC元件以增加其頻寬。切換式放大器則採用遲滯控制,其中零點尖峰之遲滯比較器可降低迴路的時間延遲。 論文中封包追蹤混合式電源調變器乃以台積電0.18微米之互補式金氧半導體製程實現,使用3.3伏特I/O元件。其供應電壓為3.5伏特且晶片面積為1.55平方毫米。為單測該電源調變器,負載端掛上6歐姆電阻並聯150 pF電容以模擬功率放大器之負載。其功率轉換效率在29.3 dBm輸出功率下達到75.2%;為量測封包追蹤之系統,採用一商用功率放大器模組以為測試用。系統之功率附加效率在22 dBm輸出功率下自8.3%改善至25.6%,此時功率增益為34.9 dB。 Since the Long-Term Evolution (LTE) was developed for the 4G communication protocol, power efficiency of the RF power amplifiers (PA) has become a more severe issue for design of the RF transmitters. The envelope tracking (ET) technique provides a useful solution to improve the PA power efficiency by modulating the power supply based on the envelope input. Therefore, the power loss can be reduced significantly compared to the stand-alone PA with fixed power supply. In this thesis, the hybrid supply modulator (HSM) is adopted to realize the ET technique. The HSM consists of a linear amplifier (LA) to track the envelope input rapidly and provide low output impedance to suppress noise or non-linearity, followed by a switching amplifier (SA) to provide most of the output power for high efficiency. The LA consists of a current-recycling OTA and an IQ-controlled Class-AB output, while the feedback path contains RC pair for bandwidth extension. The SA operates under hysteresis control with a zero-peaked hysteresis comparator for less time delay in the control loop. The presented ETHSM in this thesis is implemented in a TSMC 0.18-µm CMOS process with 3.3-V I/O devices. The supply voltage is 3.5 V and the chip occupies 1.55-mm2 area. For the ETHSM alone, the load contains a 6-Ω resistance in parallel with 150-pF capacitance to emulate the PA. The power efficiency reaches 75.2% at peak output power of 29.3 dBm. For the ET system, a commercial PA module is employed for testing. The power-added efficiency improves from 8.3% to 25.6% at 22-dBm output power with 34.9-dB power gain. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7109 |
DOI: | 10.6342/NTU202000388 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
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