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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳士元(Shih-Yuan Chen) | |
dc.contributor.author | Bo-Kai Yang | en |
dc.contributor.author | 楊博凱 | zh_TW |
dc.date.accessioned | 2021-06-17T04:30:41Z | - |
dc.date.available | 2020-08-16 | |
dc.date.copyright | 2018-08-16 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018-08-13 | |
dc.identifier.citation | [1] H. Dogan, R. G. Meyer, and A. M. Niknejad, “Analysis and design of RF CMOS attenuators,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2269–2283, Oct. 2008.
[2] I.-K. Ju, Y.-S. Noh, and I.-B. Yom, “Ultra broadband DC-40GHz 5-bit pHEMT MMIC digital attenuator,” IEEE Microwave Conf., pp. 995-998, October 2005. [3] Jing Zhao, Bo Zhang, and Xiao feng Yang, “ A 25-30 GHz 6-bit digital attenuator with high accuracy and low insertion loss,” IEEE MTT-S, March 2016 [4] N.D. Doddamani and A.V.H. Nandi, “Design of SPDT switch, 6 bit digital attenuator, 6bit digital phase shifter for L-band T/R module using 0.7 μm GaAs MMIC technology,” in Int. Signal Process, Commun. Network. Conf., pp. 302-307, Feb. 2007. [5] Behzad Razavi, Design of Analog CMOS Integrated Circuit, 2016. [6] M. Davulcu, C. Caliskan, I. Kalyoncu, M. Kaynak, and Y. Gurbuz, “7-bit SiGe-BiCMOS step attenuator for X-band phased-array radar applications,” IEEE Microw. Compon. Lett., vol. 26, no. 8, pp. 598–600, Aug. 2016. [7] B.-H. Ku and S. Hong, “6-bit CMOS digital attenuators with low phase variations for X-band phased-array systems,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 7, pp. 1651–1663, Jul. 2010. [8] W. Ciccognani, F. Giannini, E. Limiti, and P. E. Longhi, “Compensating for parasitic phase shift in microwave digitally controlled attenuators,” Electron. Lett., vol. 44, no. 12, pp. 743–744, Jun. 2008. [9] Inkwon Ju, Youn-Sub Noh and In-Bok Yom, “Ultra Broadband DC-40GHz 5-bit pHEMT MMIC Digital Attenuator”, IEEE Microwave Conf. Euro., 2005. [10] Na Chen, “A Millimeter-wave 6-bit GaAs Monolithic Digital Attenuator with Low Insertion Phase Shift”, IEEE Microwave Conf., Oct. pp.440-443,2013. [11] Takahiro Tsushima, Hiroaki Takeuchi, and Masayuki Kimishima, “A 10 MHz-6 GHz high power high linearity 35 dB digital step attenuator MMIC using GaN HEMTs with TaON passivation”, IEEE International Symposium on RFIT, Aug. 2015. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70544 | - |
dc.description.abstract | 本論文以0.18微米互補式金氧半製程來設計並實現應用於700 MHz 以及70 MHz差分信號系統中的高精確度且低損耗之數位衰減器。論文最主要的貢獻在於提出一種有別於現今普遍的衰減器電路架構,此架構可消除切換衰減狀態時所造成的級間阻抗變化之影響,提高不同衰減位元間的隔離度,進而提升各階衰減量之精確度,同時也可把一般衰減器中常見的高介入損耗改善到幾乎為零。本論文所設計完成工作於70 MHz的原型電路,其衰減量精確度能夠達到0.015 dB以內(最高衰減量為71.25 dB),700 MHz原型電路則可達到0.2 dB以內(最高衰減量為45 dB)。 | zh_TW |
dc.description.abstract | This thesis presents the design and implementation of differential-feed digital attenuators with high accuracy and low insertion loss using TSMC 0.18-m CMOS process for operation at the 700- and 70-MHz bands, respectively. The main contribution of this thesis lies in the proposal of a novel attenuator topology different from conventional ones. With this new topology, the influence of inter-stage, or inter-bit, impedance variation during ON/OFF switching state can be eliminated. It not only provides high isolation between adjacent attenuation bit but also helps reduce the insertion loss due to the inter-stage matching circuit that would otherwise be used. Importantly, the attenuation accuracy is significantly improved thanks to the excellent inter-bit isolation. The insertion loss can be almost 0 dB. The attenuation accuracy of the 70-MHz prototype circuit is within 0.015 dB (the maximum attenuation level is 71.25 dB). Meanwhile, for the 700-MHz prototype circuit, the attenuation accuracy is within 0.2 dB (the maximum attenuation level is 45 dB). | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T04:30:41Z (GMT). No. of bitstreams: 1 ntu-107-R05942026-1.pdf: 12346763 bytes, checksum: d22a01110291dcf9ffdfb6d039f1cb55 (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Literature Survey 2 1.3 Contribution 4 1.4 Chapter Outline 5 Chapter 2 Digital Attenuator Circuit Design 6 2.1 Introduction 6 2.2 Conventional Digital Attenuator 7 2.2.1 Design of Conventional Digital Attenuator 7 2.2.2 Simulation Result 9 2.3 Design and Analysis of Digital Attenuation Unit 12 2.4 Inter-Stage Connecting Circuit Design 14 2.4.1 Circuit Design and Analysis 14 2.4.2 Common-Mode Feedback Network 21 2.4.3 Proposed Inter-Stage Connecting Circuit and Attenuator Topology 23 2.5 Overall Digital Attenuator Topology 26 Chapter 3 Pre-Simulation and Post-Simulation 29 3.1 Schematic and Pre-Simulation 30 3.1.1 DA1/DA2 30 3.1.2 STAS/STAM 34 3.1.3 IFatt 37 3.1.4 STC 41 3.2 Layout and Post-Simulation 46 3.2.1 Proposed Inter-Stage Connecting Circuit 46 3.2.2 Layout of Attenuation Unit 48 3.2.3 DA1/DA2 50 3.2.4 STAS/STAM 52 3.2.5 IFatt 54 3.2.6 STC 56 3.3 Test Kit Layout and Simulation Result 60 3.3.1 Test Kit of DA1/DA2 60 3.3.2 Test Kit of STC 63 3.3.3 Test Kit of IFgain 67 Chapter 4 70-MHz System Integration 71 4.1 Pre-Simulation 71 4.2 Post-Simulation 77 Chapter 5 Conclusion and Future Work 83 5.1 Conclusion 83 5.2 Future Work 84 REFERENCE 86 附錄 (Appendix) 88 | |
dc.language.iso | zh-TW | |
dc.title | 以0.18微米互補式金氧半製程實現高精確度且低損耗之差動饋入數位衰減器 | zh_TW |
dc.title | High-Accuracy, Low-Loss Digital Attenuator with Differential Feed Using 0.18-μm CMOS Process | en |
dc.type | Thesis | |
dc.date.schoolyear | 106-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蔡作敏(Zuo-Min Tsai),歐陽良昱 | |
dc.subject.keyword | 數位衰減器,差動饋入,高精確度, | zh_TW |
dc.subject.keyword | differential feed,digital attenuators,high accuracy, | en |
dc.relation.page | 98 | |
dc.identifier.doi | 10.6342/NTU201803146 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2018-08-13 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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