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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70536完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Yu-Lun Hsieh | en |
| dc.contributor.author | 謝雨倫 | zh_TW |
| dc.date.accessioned | 2021-06-17T04:30:28Z | - |
| dc.date.available | 2028-08-12 | |
| dc.date.copyright | 2018-08-14 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-08-13 | |
| dc.identifier.citation | [1] J. Márkus, Higher-order incremental delta-sigma analog-to-digital converters, Master Thesis, 2005.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70536 | - |
| dc.description.abstract | 增量型三角積分調變器有許多應用，包含生物醫學測量、感測器陣列測量，並適用於任何多通道感測平台，這些物聯網的應用通常結合高速傳輸與無線網路連結的特性，因此低功率消耗是首先要被考慮的。此論文呈獻一個三階五位元連續時間增量型三角積分調變器，為了低功耗的考量，我們使用更有效率的連續漸進式暫存類比數位轉換器取代傳統的快閃式類比數位轉換器並且利用雜訊耦合的技術減少使用消耗功率的運算放大器之數量且達到相同的雜訊成型效果，迴路延遲補償也嵌入在連續漸進式暫存類比數位轉換器而不需要額外的數位類比轉換器。本晶片使用台積電四十奈米互補式金屬氧化物半導體1P6M製程所實現，本晶片操作於一百六十萬取樣頻率，並於二十五千赫茲的有效頻寬下於增量型模式得到71.98 dB的訊號雜訊失真比，於三角積分模式下得到72.34 dB的訊號雜訊失真比。在1.2伏特和1.5伏特的電源供應下總共消耗225微瓦，晶片的核心面積小於0.318平方毫米。 | zh_TW |
| dc.description.abstract | Incremental delta-sigma data converter (IDC) has many useful applications including biomedical measurement and sensor array measurement, and is suitable for multi-channel platforms. This application for internet of things (IOT) always combine the characteristics of high-speed transmission and wireless network connectivity. Therefore, low power consumption is the first to be considered.This thesis presents a 3rd-order, 5-bit continuous-time incremental delta-sigma data converter (CTIDC). For low power consideration, we replace conventional FLASH ADC by power-efficient successive-approximation-register (SAR) ADC and utilizing the noise coupling (NC) technique to reduce the numbers of power-hungry op-amps for the same noise shaping effect. The excess loop delay compensation (ELDC) is also embedded in the SAR ADC without using additional DAC.Fabricated in TSMC 40 nm LP 1P6M technology, the proposed modulator is operated at 1.6MHz sampling clock. It achieves peak SNDR of 71.98 dB in IDC mode and 72.34 dB SNDR in SDM mode within 25 kHz signal bandwidth. This chip dissipates 225 μW from 1.2V/1.5V supply voltage. The active area of this modulator occupies less than 0.318mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T04:30:28Z (GMT). No. of bitstreams: 1 ntu-107-R03943027-1.pdf: 4298951 bytes, checksum: 6a46b891170f9cee0fec8de400cca4e7 (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 致謝 i
摘要 iii Abstract v Contents vii List of Figures x List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation and Research Goals 1 1.2 Thesis Organization 4 Chapter 2 Fundamentals of CTIDC 5 2.1 Introduction 5 2.2 ADC Performance Metrics 5 2.2.1 Signal-to-Noise Ratio (SNR) 5 2.2.2 Signal-to-Noise-and-Distortion Ratio (SNDR) 7 2.2.3 Effective Number-of-Bits (ENOB) 7 2.2.4 Spurious-Free Dynamic Range (SFDR) 8 2.2.5 Figure of Merit (FoM) 9 2.3 Introduction to IDC 9 2.4 Fundamental of IDC 11 2.5 DT-CT Modulator Equivalence 14 2.6 Comparison Between DT and CT IDC 16 Chapter 3 Behavior Simulation and Analysis for CTIDC 17 3.1 Introduction 17 3.2 Systematic Design of Loop-Filter 17 3.3 Excess Loop Delay and DT-CT Transformation 22 3.4 Dynamic Range Scaling 24 3.5 Time-domain Analysis 25 3.6 Input-Referred Noise of Incremental ΔΣ Modulator 27 3.7 Commonly-Used ELD Compensation Architecture 29 3.8 Noise Analysis 32 3.9 Non-Ideal Behavior Analysis 34 3.9.1 Coefficients Variation Effect 34 3.9.2 Finite DC Gain of Op-Amp 35 3.9.3 Finite Gain Bandwidth Product (GBW) of Op-Amp 36 3.9.4 Effect of Input S/H Circuit 37 3.10 Current DAC Mismatch 40 Chapter 4 Circuit Implementation of CTIDC 43 4.1 Introduction 43 4.2 Proposed Modulator Architecture 43 4.3 Circuit Level Parameters 45 4.4 Op-amp Design 45 4.5 Current DAC 52 4.5.1 DAC Biasing Circuit and DAC Cell 52 4.5.2 DAC Driving Circuit 54 4.6 Quantizer Design 55 4.6.1 Incorporating SAR ADC and NC Caps Into System 55 4.6.2 ELD Compensation 63 4.7 RC Time Constant Tuning 65 4.8 Clock Generator 66 4.9 DWA 68 4.10 Layout Floor Plan 70 4.11 Post-Layout Simulation 72 Chapter 5 Experimental Results 73 5.1 Introduction 73 5.2 Measurement Setup 74 5.3 Print Circuit Board Design 75 5.4 Measurement Results 76 5.5 Performance Summary 78 5.6 Conclusions and Future Works 80 Bibliography 81 | |
| dc.language.iso | en | |
| dc.subject | 連續漸進式暫存類比數位轉換器 | zh_TW |
| dc.subject | 連續時間增量型三角積分調變器 | zh_TW |
| dc.subject | 雜訊耦合 | zh_TW |
| dc.subject | 迴路延遲補償 | zh_TW |
| dc.subject | SAR ADC | en |
| dc.subject | Continuous-time incremental delta-sigma data converter | en |
| dc.subject | Noise coupling | en |
| dc.subject | Excess loop delay compensation | en |
| dc.title | 連續時間增量型三角積分調變器 | zh_TW |
| dc.title | Continuous-Time Incremental Delta Sigma Data Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃柏鈞(Po-Chiun Huang),林宗賢(Tsung-Hsien Lin) | |
| dc.subject.keyword | 連續時間增量型三角積分調變器,連續漸進式暫存類比數位轉換器,雜訊耦合,迴路延遲補償, | zh_TW |
| dc.subject.keyword | Continuous-time incremental delta-sigma data converter,SAR ADC,Noise coupling,Excess loop delay compensation, | en |
| dc.relation.page | 85 | |
| dc.identifier.doi | 10.6342/NTU201803065 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-08-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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