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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70467
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dc.contributor.advisor李建模
dc.contributor.authorHeng-Yi Linen
dc.contributor.author林恆毅zh_TW
dc.date.accessioned2021-06-17T04:28:49Z-
dc.date.available2021-09-01
dc.date.copyright2018-08-18
dc.date.issued2018
dc.date.submitted2018-08-13
dc.identifier.citation[Bhamidipati 2017] Bhamidipati, Lakshmi, et al. “A Power Delivery Network and Cell Placement Aware IR-drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews,” VLSI (ISVLSI), 2017 IEEE Computer Society Annual Symposium on. IEEE, 2017.
[Chen 1997] H. Chen and D. Ling, “Power supply noise analysis methodology for deep submicron VLSI design,” Proceedings of ACM/IEEE Design Automation Conf., pp. 638–643, 1997.
[Chen 2001] T.-H. Chen, and Charlie C.-P. Chen, “Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods,” Proc. of the 38th annual Design Automation Conf., 2001, Pages 559-562.
[Chen 2008] Chen, Po-Yuan, Che-Yu Liu, and TingTing Hwang. “Transition-aware decoupling-capacitor allocation in power noise reduction,” Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design. IEEE Press, 2008.
[Chen 2016] Chen, Tianqi, and Carlos Guestrin. 'Xgboost: A scalable tree boosting system.' Proc. 22nd acm sigkdd int’l conf. on knowledge discovery and data mining. ACM, 2016. p. 785-794.
[Feng 2008] Z. Feng, and P. Li, “Multigrid on GPU: Tackling Power Grid Analysis on Parallel SIMT Platforms,” Proc. IEEE/ACM Int’l Conf. Computer-Aided Design (ICCAD’08), Nov. 2008, pp. 647-654.
[Fang 2018] Fang, Yen-Chun, et al. “Machine-learning-based Dynamic IR Drop Prediction for ECO,” ICCAD, 2018. (Accepted)
[Ho 1975] Ho, Ruehi, and Brennan, “The Modified Nodal Approach to Network Analysis,” Proc. IEEE Transactions on Circuits and Systems, 1975.
[Jiang 1999] Y. M. Jiang and K. T. Cheng, “Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices,” Proceedings of ACM/IEEE Design Automation Conf., pp.760-765, 1999.
[Kozhaya 2002] J. N. Kozhaya, et al., “A multigrid-like technique for power grid analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Oct. 2002, volume:21, issue:10.
[Li 2013] Y.-H. Li, W.-C. Lien, I.-C. Lin, and K.-J. Lee, “Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing,” IEEE Trans. on Computer-Aided Design, 2013, vol. 33, No. 1, 127-138.
[Li 2018] Li, Yu-Ching, et al. “Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations,” VLSI Design, Automation and Test (VLSI-DAT), 2018 International Symposium on. IEEE, 2018.
[Ma 2009] J. Ma, J. Lee, and M. Tehranipoor, “Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths,” Proc. of VLSI Test Symposium, 2009, pp. 221-226.
[Nassif 2000] S. R. Nassif, and J. N. Kozhaya, “Fast Power Grid Simulation,” IEEE Design Automation Conference, 2000, Jun., pp. 156-161.
[Nassif 2008] S. Nassif., “Power grid analysis benchmarks,” Asia and South Pacific Design Automation Conference, Mar. 2008, pages 376–381.
[Okumura 2010] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, M. Hashimoto, “Gate Delay Estimation in STA under Dynamic Power Supply Noise,” Proc. ASPDAC., 2010.
[Qian 2003] H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Random Walks in a Supply Network,” Proceedings of the IEEE/ACM Design Automation Conference, June 2003, pp. 93–98.
[RedHawk 2016] ANSYS RedHawk, “https://www.apache-da.com/products/redhawk/redhawk-resources”
[Saleh 2000] R. Saleh, S. Z. Hussain, S. Rochel, and D. Overhauser, “Clock skew verification in the presence of IR-drop in the power distribution network,” IEEE Trans. on Computer-Aided Design, vol. 19, No. 6, pp. 635–644, 2000.
[Shepard 1996] K. L. Shepard and V. Narayanan, “Noise in deep submicron digital design,” Proceedings of IEEE ICCAD, pp. 524–531, 1996.
[Tehranipoor 2010] M. Tehranipoor and K.M. Butler, “Power Supply Noise: A Survey on Effects and Research,” IEEE Design & Test of Computers, vol.27, issue 2, 2010, pp. 51-67.
[Tweaker 2017] Dorado Tweaker ECO, “http://www.dorado-da.com/”
[Tseng 2014] Tseng, Tsu-Wei, et al. “A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage,” VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on. IEEE, 2014.
[Wang 2006] J. Wang, D. M. H. Walker, A. Majhi, B. Kruseman, G. Gronthoud, L. E. Villagra, P. v. d. Wiel, and S. Eichenberger, “Power supply noise in delay testing,” Proc. of Int’l Test Conf., 2006, pp. 1-10.
[Zhong 2005] Y. Zhong, and M. D. F. Wong, “Fast Algorithms for IR Drop Analysis in Large Power Grid,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Nov. 2005, pp. 351–357.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70467-
dc.description.abstract本論文提出一種通過工程修改命令(Engineering Change Order or ECO)修復電路壓降違規的自動化流程。 我們的工程修改命令技術提供元件(cell)移動(move)和縮小尺寸(downsize)的解決方案。 我們使用機器學習來預測電路壓降,以便我們可以防止過度修理。 我們使用商業軟體來預測時序,所以這是一個時序感知的工程修改命令。 通過以上兩個預測,我們提出了一種新穎的多輪二分匹配,以優化工程修改命令之資源利用率。 實驗結果顯示,對於500萬元件的實際設計,我們提出的方法修復了原始11,555個違規元件(violation cell)中的2,504(22%)個違規元件,並修復了原始98,674 mV總過量電路壓降中的36,272 mV(37%)總過量電路壓降。 我們能夠在13個小時內對7千個元件進行工程修改命令,因此我們的工程修改命令流程非常實用,可以應用於大型工業設計。zh_TW
dc.description.abstractThis thesis proposes an automatic flow to repair IR-drop violations by Engineering Change Order (ECO). Our ECO technique provides cell move and downsize solutions. We use machine learning to predict IR-drop so that we can prevent over-fixing. We use a commercial tool to predict timing so that this is a timing-aware ECO. With the above two predictions, we propose a novel multi-round bipartite matching to optimize the ECO resource utilization. Experimental results show that for a 5M gate real design, our proposed method repairs 2,504 (22%) violation cells out of the original 11,555 violation cells and repairs 36,272 mV (37%) total excessive IR out of the original 98,674 mV total excessive IR. We are able to perform ECO on seven thousand cells within 13 hours, so our ECO flow is practical and can be applied to large industrial designs.en
dc.description.provenanceMade available in DSpace on 2021-06-17T04:28:49Z (GMT). No. of bitstreams: 1
ntu-107-R05943084-1.pdf: 1690401 bytes, checksum: 4a2c5b9a4f6e036813d2799c764bc25d (MD5)
Previous issue date: 2018
en
dc.description.tableofcontents誌謝 i
中文摘要 ii
ABSTRACT iii
CONTENTS iv
LIST OF FIGURES vi
LIST OF TABLES vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Proposed technique 2
1.3 Contribution 3
1.4 Our assumptions 4
1.5 Organization 4
Chapter 2 Background 5
2.1 Prior work of IR-drop ECO 5
2.2 Machine learning IR-drop prediction 9
2.3 IR-drop analysis 10
Chapter 3 Proposed Techniques 11
3.1 Flow 11
3.2 Define ECO region, IR hotspot and IR coldspot windows 12
3.3 Predict IR-drop contribution 16
3.4 Pre-move 17
3.5 Multi-round bipartite matching 19
3.6 Downsize 25
Chapter 4 Experimental Results 26
4.1 Experimental setup 26
4.2 IR-drop results 30
4.3 Timing results 34
4.4 Run time 35
Chapter 5 Discussion 36
Chapter 6 Conclusion 38
References 39
Appendix 42
dc.language.isoen
dc.subject電路壓降zh_TW
dc.subject工程修改命令zh_TW
dc.subject機器學習zh_TW
dc.subjectIR-dropen
dc.subjectECOen
dc.subjectmachine learningen
dc.title使用機器學習之自動化電路壓降工程修改命令zh_TW
dc.titleAutomatic IR-Drop ECO Using Machine Learningen
dc.typeThesis
dc.date.schoolyear106-2
dc.description.degree碩士
dc.contributor.oralexamcommittee陳中平,方家偉
dc.subject.keyword電路壓降,工程修改命令,機器學習,zh_TW
dc.subject.keywordIR-drop,ECO,machine learning,en
dc.relation.page43
dc.identifier.doi10.6342/NTU201803107
dc.rights.note有償授權
dc.date.accepted2018-08-13
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
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