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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70421完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Han-Chun Chen | en |
| dc.contributor.author | 陳翰群 | zh_TW |
| dc.date.accessioned | 2021-06-17T04:27:49Z | - |
| dc.date.available | 2019-08-19 | |
| dc.date.copyright | 2018-08-19 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-08-13 | |
| dc.identifier.citation | [1] R. Wu, K. A. A. Makinwa and J. H. Huijsing, 'A Chopper Current-Feedback Instrumentation Amplifier with a 1mHz 1/f Noise Corner and an AC-Coupled Ripple Reduction Loop,' IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3232-3243, 2009.
[2] R. Wu, J. H. Huijsing and K. A. A. Makinwa, 'A Current-Feedback Instrumentation Amplifier with a Gain Error Reduction Loop and 0.06% Untrimmed Gain Error,' IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2794-2806, 2011. [3] R. Wu, Y. Chae, J. H. Huijsing and K. A. A. Makinwa, 'A 20b ±40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers,' IEEE Journal of Solid-State Circuits, vol. 47, no. 9, pp. 2152-2163, 2012. [4] G. Singh, R. Wu, Y. Chae and K. A. A. Makinwa, 'A 20bit continuous-time ΣΔ modulator with a Gm-C integrator, 120dB CMRR and 15 ppm INL,' in Proceedings of the IEEE Europian Solid-State Circuits Conference, Bordeaux, 2012. [5] C. C. Tu, Y. K. Wang and T. H. Lin, 'A Low-Noise Area-Efficient Chopped VCO-Based CTDSM for Sensor Applications in 40-nm CMOS,' IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2523-2532, 2017. [6] C. C. Tu, Y. K. Wang and T. H. Lin, 'A 0.06mm2 ± 50mV range −82dB THD chopper VCO-based sensor readout circuit in 40nm CMOS,' in IEEE Symposium on VLSI Circuits, Kyoto, 2017. [7] M. Z. Straayer and M. H. Perrott, 'A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping,' IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1089-1098, 2009. [8] M. Park and M. H. Perrott, 'A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time DeltaSigma ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 um CMOS,' IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3344-3358, 2009. [9] N. Maghari and U. K. Moon, 'A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer,' in IEEE International Solid-State Circuits Conference, San Francisco, CA, 2011. [10] C. C. Tu, F. W. Lee, H. C. Chen, Y. K. Wang and T. H. Lin, 'An area-efficient capacitively-coupled sensor readout circuit with current-splitting OTA and FIR-DAC,' in IEEE Asian Solid-State Circuits Conference, Seoul, 2017. [11] P. Prabha, S. J. Kim, K. Reddy, S. Rao, N. Griesert, A. Rao, G. Winter and P. K. Hanumolu, 'A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications,' IEEE Journal of Solid-State Circuits, vol. 50, no. 8, pp. 1785-1795, 2015. [12] R. Mohan, S. Zaliasl, G. Gielen, C. V. Hoof, N. V. Helleputte and R. F. Yazicioglu, 'A 0.6V 0.015mm2 time-based biomedical readout for ambulatory applications in 40nm CMOS,' in IEEE International Solid-State Circuits Conference, San Francisco, CA, 2016. [13] S. Dey, K. Reddy, K. Mayaram and T. S. Fiez, 'A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta–Sigma Modulator With VCO Quantizer Nonlinearity Cancellation,' IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 799-813, 2018. [14] Q. Fan, F. Sebastiana, J. H. Huijsing and K. A. A. Makinwa, 'A 1.8uW 1uV-Offset Capacitively-Coupled Chopper Instrumentation Amplifier in 65nm CMOS,' IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1534-1543, 2011. [15] M. Z. Straayer and M. H. Perrott, 'An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC,' in IEEE Symposium on VLSI Circuits, Honululu, HI, 2008. [16] S. Yoder, M. Ismail and W. Khalil, 'VCO-Based Quantizer,' in VCO-Based Quantizers Using Frequency-to-Digital and Time-to-Digital Converters, Springer Science + Business Media, 2011, pp. 9-29. [17] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2001. [18] R. Muller, S. Gambini and J. M. Rabaey, 'A 0.013 mm2, 5uW , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply,' IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 232-243, 2012. [19] A. A. Abidi, 'Phase Noise and Jitter in CMOS Ring Oscillator,' IEEE Journal of Solid-State Circuit, vol. 41, no. 8, pp. 1803-1816, 2006. [20] C. C. Enz and G. C. Temes, 'Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization,' Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1615, 1996. [21] P. G. Drennan and C. C. McAndrew, 'Understanding MOSFET Mismatch for Analog Design,' IEEE Journal of Solid-State Circuit, vol. 38, no. 3, pp. 450-456, 2003. [22] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converter, NY: Wiley Interscience, 2005. [23] Y. Yoon, K. Lee, S. Hong, X. Tang, L. Chen and N. Sun, 'A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration,' in IEEE Custom Integrated Circuits Conference, San Jose, 2015. [24] K. Lee, Y. Yoon and N. Sun, 'A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLA,' in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, 2011. [25] T. Kim, C. Han and N. Maghari, 'An 11.4mW 80.4dB-SNDR 15MHz-BW CT delta-sigma modulator using 6b double-noise-shaped quantizer,' in IEEE International Solid-State Circuits Conference, San Francisco, 2017. [26] N. V. Helleputte, 'A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP,' IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 230-244, 2015. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70421 | - |
| dc.description.abstract | 感測器系統扮演著人類和機器之間的橋樑，隨著物聯網和人工智慧的演進感測器系統也越來越重要。此外，隨著半導體工業的進步，我們也希望能夠將龐大的電路系統實現在單一晶片中，本論文著重探討應用於此系統的類比前端電路設計。此電路的主要任務為將振幅極小且低頻的感測器信號直接轉換為數位訊號，並希望在電壓和功率消耗的限制下，有足夠的頻寬和訊噪比。傳統的感測器介面電路係由一個低雜訊放大器加上一個類比數位轉換器所組成，不論在功率及面積方面都較沒效率，在電路的設計上也比較複雜，為了解決上述這些問題，本篇採用兩組電壓控制震盪器來實現兩階的連續時間三角積分調變器，為一個有類比前端特性的連續時間類比數位轉換器。
本論文對我們所設計的連續時間三角積分轉換器做了實作及量測，此電路實作於台積電一百八十奈米製程。這個作品將第一級積分過的訊號藉由第二級由電壓控制震盪器所構成的量化器做量化，由於量化器本身具有一階三角積分調變的特性，故整個迴路會有兩階的三角積分調變，且此量化器的數位輸出為一個經動態單元匹配後的訊號可以提升電容式數位類比轉換器的線性度，故不需要再加上動態權重平均電路，而能有較大的頻寬。此電路之核心晶片面積為零點一九毫米平方，本晶片工作於一百萬赫茲的取樣頻率下並使用一點二伏特的供給電壓，在六千赫茲的頻寬下的訊雜扭曲比為六十二點五分貝，整個電路的功率消耗為五十三點八微瓦，質量指標為一百四十三點七分貝。經過量測證實此晶片能符合低頻感測前端電路的需求，並在能量效率及晶片面積上有很好的表現。 | zh_TW |
| dc.description.abstract | Sensor systems are becoming more and more important with the progress of IOT and AI. Besides, we hope to integrate whole sensors system which includes sensor interface circuit and digital processor in one chip. Therefore, this thesis focuses on the power and area efficient analog front end (AFE) design. Conventional sensor interface circuit consists of a low noise amplifier and an analog to digital converter (ADC). It is inefficient on both power consumption and area, and also complex to design. To solve the above problem, this thesis uses two voltage control oscillator (VCO) based circuits as the integrator and quantizer to implement the 2nd-order continuous time delta-sigma modulator (CTDSM), merging an ADC with the AFE.
This thesis implements and measures the CTDSM in TSMC 180 nm CMOS process. This work uses a VCO and a counter as an integrator. Furthermore, we add another VCO with frequency-to-digital converter as a quantizer. Due to the first-order noise shaping characteristic of the second-stage. The whole loop shows second-order noise shaping. The second-stage quantizes the signal as a digital thermometer code with dynamic element matching (DEM), we do not need the dynamic weighted averaging (DWA). The core area of the chip is 0.19 mm2. This chip using sampling frequency at 1 MHz, with supply voltage of 1.2 V. This chip achieves the signal-to-noise-and-distortion-ratio of 62.5 dB. The power consumption of this chip is 52.4 μW, and the FoMs of the work is 143.7 dB. This chip meets bio-AFE requirement and is outstanding on power consumption and chip area. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T04:27:49Z (GMT). No. of bitstreams: 1 ntu-107-R04943143-1.pdf: 4070126 bytes, checksum: f7acfff817435c3c3159f3274bacca7c (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 致謝 viii
摘要 ix Abstract xi Table of Contents xiv List of Figures xvii List of Tables xx Chapter 1 Introduction 1 1.1 Motivation 1 1.1.1 Sensor Readout Circuit 1 1.1.2 Architecture of Sensor Readout Circuit 3 1.2 Thesis Overview 5 Chapter 2 Instrumentation Amplifier and Continuous Time Delta-Sigma Modulator Design in Analog Front-End 6 2.1 Introduction of the Instrumentation Amplifier 6 2.1.1 Instrumentation Amplifier Design 6 2.1.2 Non-ideality in the Bio-sensor and the choppers 9 2.2 Delta-Sigma Modulator 11 2.2.1 Introduction of delta-sigma modulator 11 2.2.2 Model of delta-sigma modulator 13 2.2.3 Second order delta-sigma modulator 15 2.3 AFE with IA and DSM 16 2.3.1 AFE with a CFIA and a DTDSM (JSSC 2012) [3] 17 2.3.2 Gm-C CTDSM (ESSCIRC 2012) [4] 18 2.4 Summary 19 Chapter 3 Voltage Control Oscillator Introduction and Application 21 3.1 VCO Characteristic 21 3.2 VCO-based Integrator 24 3.2.1 Limitation of the Gm-C integrator 24 3.2.2 Principle of the VCO-based Integrator 26 3.3 VCO Quantizer 28 3.3.1 Noise-shaped Integrating Quantizer 28 3.3.2 Use Frequency-to-Digital Converter (FDC) as an Quantizer 29 3.3.3 Dynamic element matching by FDC VCO-based quantizer 33 Chapter 4 Architectures of 2nd-Order VCO-Based DSM 35 4.1 System Architecture 35 4.2 Building Blocks 38 4.2.1 First Stage Gm-CCO 38 4.2.2 Barrel-shift Counter 41 4.2.3 Digitally Controlled Oscillator 45 4.2.4 FDC Quantizer and Output Stage 46 4.2.5 Feedback DAC Circuit 48 4.3 System Simulation Results 50 4.3.1 FFT Simulation result 50 Chapter 5 Experimental Result of the 2nd-Order VCO-Based CTDSM 53 5.1 Chip photo 53 5.2 Testing Setup 54 5.3 PCB Board 55 5.4 Measurement Result 55 5.4.1 Power Measurement 55 Chapter 6 Future Works 63 6.1 Eliminate CCO’s offset 63 6.2 DCO auto calibration 63 6.3 DC servo loop & Ripple reduction loop 63 6.4 Eliminate the nonlinearity of VCOQ 64 | |
| dc.language.iso | zh-TW | |
| dc.subject | 電壓控制震盪器 | zh_TW |
| dc.subject | 低頻前端電路 | zh_TW |
| dc.subject | 三角積分調變器 | zh_TW |
| dc.subject | delta-sigma modulation | en |
| dc.subject | voltage control oscillator | en |
| dc.subject | Analog front end | en |
| dc.title | 應用於低頻感測系統之兩階電壓控制震盪器連續時間三角積分類比前端電路設計 | zh_TW |
| dc.title | Design of Voltage-Controlled-Oscillator-Based Continuous-Time Delta-Sigma Analog Front-End Circuit for Low Frequency Sensing Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳信樹(Hsin-Shu Chen),彭盛裕(Sheng-Yu Peng) | |
| dc.subject.keyword | 低頻前端電路,電壓控制震盪器,三角積分調變器, | zh_TW |
| dc.subject.keyword | Analog front end,voltage control oscillator,delta-sigma modulation, | en |
| dc.relation.page | 68 | |
| dc.identifier.doi | 10.6342/NTU201803204 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-08-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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