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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Po-Wei Chen | en |
| dc.contributor.author | 陳柏瑋 | zh_TW |
| dc.date.accessioned | 2021-06-17T04:27:45Z | - |
| dc.date.available | 2021-08-18 | |
| dc.date.copyright | 2018-08-18 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-08-13 | |
| dc.identifier.citation | [Abramovici 83] M. Abramovici, P. R. Menon, and D. T. Miller, “Critical Path Tracing: An Alternative to Fault Simulation,” in Proc. of Design Automation Conference, pp. 214-220, 1983.
[Akers 90] S. B. Akers, B. Krishnamurthy, S. Park, and A. Swaminathan, “Why is less information from logic simulation more useful in fault simulation?,” in Proc. of International Test Conference, pp. 786–800, 1990. [Chao 14] S.-M. Chao, P.-J. Chen, J.-Y. Chen, P.-H. Chen, A.-F. Lin, J. C.-M. Li, et al., “Divide and conquer diagnosis for multiple defects,” in Proc. International Test Conference, pp. 1-8, 2014. [Chen 14] P.-J. Chen, C.-C. Che, J. C.-M. Li, S.-F. Kuo, P.-Y. Hsueh, C.-Y. Kuo, and J.-N. Lee, “Physical-aware Systematic Multiple Defect Diagnosis,“ lET Computers & Digital Techniques, pp. 199-209, 2014. [Singh 14] E. Singh, “Analytical modeling of 3D stacked IC yield from wafer to wafer stacking with radial defect clustering,” in Proc. of 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, pp. 26-31, 2014. [Girard 92] P. Girard, C. Landrault, and S. Pravossudovitch, “A novel approach to delay-fault diagnosis,” in Proc. of 29th Design Automation Conference, pp. 357–360, 1992. [Huisman 04] L. M. Huisman, “Diagnosing Arbitrary Defects in Logic Designs using Single Location at a Time (SLAT),” in Proc. of IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, pp. 91-101, 2004. [Kin 16] B. Kim, Y.-S. Jeong, S. H. Tong, I.-K. Chang, and M.-K. Jeong, “Step-down spatial randomness test for detecting abnormalities in DRAM wafers with multiple spatial maps,” in Proc. of IEEE Transactions on Semiconductor Manufacturing, pp. 57-65, 2016. [Mentor 11] “FastScan and FlexTest Reference Manual,” Mentor Graphics, 2011. [Nangate 09] “Nangate 45nm Open Cell Library,” Nangate, 2009. [Peng 10] K. Peng, Y. Huang, R. Guo, W.-T. Cheng, and M. Tehranipoor, “Emulating and diagnosing IR-drop by using dynamic SDF,” in Proc. of the 2010 Asia and South Pacific Design Automation Conference, pp. 511-516, 2010. [Pomeranz 11] I. Pomeranz, “Diagnosis of transition fault clusters,” in Proc. of Design Automation Conference, pp. 429-434, 2011. [Venkataraman 01] S. Venkataraman, and S. B. Drummonds, “POIROT: Applications of a Logic Fault Diagnosis Tool,” IEEE Design & Test of Computers, pp. 19-30, 2001. [Wang 05] Z. Wang, M. M. Marek-Sadowska, K.-H. Tsai, and J. Rajski, “Delay-fault diagnosis using timing information,” IEEE transactions on computer-aided design of integrated circuits and systems, pp. 1315-1325, 2005. [Wang 06] Z. Wang, M. Marek-Sadowska, K.-H. Tsai, J. Rajski, “Analysis and Methodology for Multiple-Fault Diagnosis,” IEEE Transactions. on Computer-aided Design of Integrated Circuits and Systems, pp. 558-575, 2006. [Ye 10] J. Ye, Y. Hu, and X. Li, “Diagnosis of multiple arbitrary faults with mask and reinforcement effect, ” in Proc. of Design Automation and Test in Europe, pp. 885-890, 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70418 | - |
| dc.description.abstract | 在先進的製程中，晶片上的缺陷容易群聚在小區域。另外，局部電壓壓降也會造成部分區域的延遲錯誤。然而傳統診斷技術無法有效解決群聚延遲錯誤。這篇論文針對實體群聚多重轉態延遲錯誤提出一個診斷方法。我們使用一種效果原因的追蹤技術來尋找可能的延遲錯誤候選人。 此外，我們提出了一個近似覆蓋經驗法則來尋找一群延遲錯誤候選人。這個經驗法則允許試驗故障與模擬故障有些不同，如此一來錯誤遮蔽與增強效應可能被忍受。在ISCAS'89和ITC'99的電路上，實體群聚多重轉態延遲故障實驗中顯示出我們診斷技術的能力。當插入十個實體群聚多重轉態延遲錯誤時，我們的診斷技術正確率(0.55)比商業軟體的正確率(0.24)還要高。 | zh_TW |
| dc.description.abstract | For advanced technologies, defects on a wafer tend to cluster in a small area. Also, local IR drop can cause delay faults in a small region. However, traditional diagnosis technique cannot handle clustered delay faults very well. This thesis presents a multiple fault diagnosis technique for physically-clustered transition delay faults. We use an effect-cause tracing to identify possible transition delay fault candidates. Then, we propose an approximate covering heuristic to find a group of candidate faults. This heuristic allows some difference between test failure and simulation failure so that masking effect and reinforcement effect are likely to be tolerated. Simulation on ISCAS’89 and ITC’99 benchmark circuits with physically-clustered multiple transition delay faults demonstrate the effectiveness of our diagnosis technique. The accuracy of our technique with 10 physically-clustered transition delay faults (0.55) is much higher than that of a commercial tool (0.24). | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T04:27:45Z (GMT). No. of bitstreams: 1 ntu-107-R05943085-1.pdf: 1960758 bytes, checksum: 2b6e38a050e2cdffa486053ba5646812 (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 1 Chapter 1 Introduction 1
1.1 Motivation 1 1.2 Proposed Techniques 3 1.3 Contributions 4 1.4 Assumption 6 1.5 Organization 6 2 Chapter 2 Background 7 2.1 Prior Work in Multiple Defect Diagnosis 7 2.2 Prior Work in Delay Fault Diagnosis 8 2.3 Path Tracing Technique 9 2.3.1 Critical Path Tracing 9 2.3.2 Non-critical Path Tracing 11 2.4 Masking and Reinforcement Effects 14 3 Chapter 3 Proposed Techniques 16 3.1 Overall Flow 16 3.2 Star Tracing for TDF 18 3.3 Approximate Covering Heuristic 23 3.3.1 Find Suspected Candidates 25 3.3.2 Cover Test Failures 26 4 Chapter 4 Experimental Results 30 4.1 Simulation Setup 30 4.2 Simulation Results of Multiple Faults 32 4.3 Runtime Results 37 5 Chapter 5 Discussion 38 6 Chapter 6 Conclusion and Future Work 40 7 References 42 | |
| dc.language.iso | en | |
| dc.subject | 轉態延遲錯誤診斷 | zh_TW |
| dc.subject | 多重錯誤診斷 | zh_TW |
| dc.subject | 實體群聚錯誤 | zh_TW |
| dc.subject | physically-clustered faults | en |
| dc.subject | transition delay faults diagnosis | en |
| dc.subject | multiple faults | en |
| dc.title | 適用於群聚多重轉態延遲錯誤診斷技術 | zh_TW |
| dc.title | Diagnosis Technique Suitable for Clustered Multiple Transition Delay Faults | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),呂學坤(Shyue-Kung Lu) | |
| dc.subject.keyword | 實體群聚錯誤,多重錯誤診斷,轉態延遲錯誤診斷, | zh_TW |
| dc.subject.keyword | physically-clustered faults,multiple faults,transition delay faults diagnosis, | en |
| dc.relation.page | 44 | |
| dc.identifier.doi | 10.6342/NTU201803255 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-08-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-107-1.pdf 未授權公開取用 | 1.91 MB | Adobe PDF |
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