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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
dc.contributor.author | Sheng-How Tseng | en |
dc.contributor.author | 曾聖豪 | zh_TW |
dc.date.accessioned | 2021-06-17T03:49:04Z | - |
dc.date.available | 2019-02-26 | |
dc.date.copyright | 2018-02-26 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018-01-22 | |
dc.identifier.citation | [1] R. Palmer et al., “A 14 mW 6.25 Gb/s Transceiver in 90-nm CMOS for Serial Chip-to-Chip Communications,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 440–441, Feb. 2007.
[2] G. Balamurugan et al., “A Scalable 5–15 Gb/s, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1010–1019, Apr. 2009. [3] Y. B. Luo et al., “A 250Mb/s-to-3.4Gb/s HDMI Receiver with Adaptive Loop Updating Frequencies and an Adaptive Equalizer,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 190–191. [4] J. Savoj et al., “A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2582–2594, Nov. 2013. [5] W. S. Kim et al., “A 5.4-Gbit/s Adaptive Continuous-Time Linear Equalizer Using Asynchronous Undersampling Histograms,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 59, no. 9, pp. 553-557, Sep. 2012. [6] Z. H. Hong et al., “A 3.12 pJ/bit, 19–27 Gbps Receiver with 2-Tap DFE Embedded Clock and Data Recovery,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2625–2634, Nov. 2015. [7] V. Stojanovic et al., “Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equalization and Data Recovery,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 1012–1026, Apr. 2005. [8] K.L J. Wong et al. , “Edge and Data Adaptive Equalization of Serial-Link Transceivers,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2157–2169, Apr. 2008. [9] A.C. Carusone et al., “An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 53, no. 9, pp. 807-811, Sep. 2006. [10] E. H. Chen et al., “Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2144–2156, Sep. 2008. [11] J.W. Jung and B. Razavi, “A 25Gb/s 5.8mW CMOS Equalizer,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 515-526, Feb 2015. [12] J. Savoj and B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 761-768, May 2001. [13] J. W. Jung and B. Razavi, “A 25-Gb/s 5-mW CMOS CDR/Deserializer,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 684-697, Mar 2013. [14] F. Zhong et al., “A 1.0625~14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2157–2169, Apr. 2011. [15] Y. H. Kim et al., “A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE with Single Loop Spectrum Balancing Method,” IEEE Trans. On Very Large Scale Integration Systems, vol. 24, no. 2, pp. 789–793, Apr. 2016. [16] N. Kocaman et al., “A 3.8 mW/Gbps Quad-Channel 8.5–13 Gbps Serial Link with a 5 Tap DFE and a 4 Tap Transmit FFE in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 4, pp. 881–892, Apr. 2016. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70201 | - |
dc.description.abstract | 這篇論文實作了一個使用眼寬偵測之八十億位元速率的可適性接收器,其等化器的係數可以自動調整,並使加法器輸出信號的眼寬達到最大。此接收器是使用40 奈米CMOS 製程,其面積為0.18 平方毫米。在頻道損耗為9dB、18dB 和25dB下,輸出信號的資料抖動分別為34.53ps、43.87ps 和63.64ps,而在頻道損耗為25dB的情況下,經過可適性調整後,所有量測結果的誤碼率皆低於10-11,並有著不錯的抖動容忍度,在100 MHz 的抖動容忍度為360 mUI。此接收器的總功率消耗為84mW,其功率效益比為10.5 mW/Gb/s。 | zh_TW |
dc.description.abstract | This thesis presents an 8 Gb/s adaptive receiver with eye-width detection. The equalizer parameter of the receiver is automatically calibrated by means of detecting the summer output eye-width which has the maximum eye-opening. The receiver is fabricated in 40-nm CMOS technology with an active area of 0.18 mm2. All the measured bit error rate (BER) are less the 10-11 over a 60cm PCB trace with the channel loss of 25 dB at Nyquist frequency. The measured total data jitter of the receiver is 34.53ps, 43.87ps and 63.64ps while the channel loss are 9dB, 18dB and 25dB, respectively. After adaptation, the receiver has a high jitter tolerance of 360 mUI at 100 MHz while the channel loss is 25dB. The overall power consumption of the receiver is 84 mW which converts to a power efficiency of 10.5 mW/Gb/s at 8Gb/s for the PCI-E 3.0 application. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T03:49:04Z (GMT). No. of bitstreams: 1 ntu-107-R02943038-1.pdf: 2665636 bytes, checksum: 1a01ef6bc3a35783af53ca60766516b8 (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | 1. 簡介 1
2. 使用眼寬偵測之八十億位元速率可適性接收器 5 2.1 動機 6 2.2 電路描述 7 2.2.1 系統架構 7 2.2.2 線性等化器 8 2.2.3 決策回授等化器 8 2.2.4 時脈與資料回復電路 10 2.3 可適性演算法 12 3. 模擬與量測結果 18 3.1 模擬結果 19 3.1.1 決策回授等化器電路模擬 19 3.1.2 接收器等化功能模擬 22 3.2 量測結果 27 3.2.1 接收器功能量測以及可適性演算法的驗證 27 3.2.2 眼寬偵測時間和其精準度關係的驗證 31 4. 結論與未來展望 36 4.1 結論 37 4.2 未來展望 39 參考文獻 40 | |
dc.language.iso | zh-TW | |
dc.title | 使用眼寬偵測之八十億位元速率可適性接收器 | zh_TW |
dc.title | An 8 Gb/s Adaptive Receiver with Eye-width Detection | en |
dc.type | Thesis | |
dc.date.schoolyear | 106-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),李泰成(Tai-Cheng Lee) | |
dc.subject.keyword | 等化器,可適性演算法,眼寬偵測, | zh_TW |
dc.subject.keyword | Equalizer,Adaptive algorithm,Eye-width detection, | en |
dc.relation.page | 41 | |
dc.identifier.doi | 10.6342/NTU201800127 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2018-01-23 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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