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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70073完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Ding-Kuo Lin | en |
| dc.contributor.author | 林鼎國 | zh_TW |
| dc.date.accessioned | 2021-06-17T03:42:02Z | - |
| dc.date.available | 2020-02-23 | |
| dc.date.copyright | 2018-02-23 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-02-06 | |
| dc.identifier.citation | [1] P. Harpe, E. Cantatore and A. v. Roermund, 'A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction,' 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, 2013, pp. 270-271.
[2] H. Y. Tai, Y. S. Hu, H. W. Chen and H. S. Chen, '11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS,' 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 196-197. [3] M. Ding, P. Harpe, Y. H. Liu, B. Busze, K. Philips and H. de Groot, '26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme,' 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3. [4] M.-H. Wu, et al., “A 12-bit 8.47-fJ/Conversion-Step 1-MS/s SAR ADC using Capacitor-Swapping Technique,” IEEE ASSCC Dig. Tech. Papers, pp. 157-160, Nov. 2012. [5] F. van der Goes et al., '11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS,' 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 200-201. [6] P. Harpe, E. Cantatore and A. van Roermund, '11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR,' 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 194-195. [7] T. Miki, et al., “A 4.2mW 50MS/s 13bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques,” IEEE J. Solid-State Circuits, vol. 50, no. 6, pp. 1372-1381, Jun. 2015. [8] Shuo-Wei Mike Chen and R. W. Brodersen, 'A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13/spl mu/m CMOS,' 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, San Francisco, CA, 2006, pp. 2350-2359. [9] Y. Zhu, et al., “Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC,” IEEE Trans Very Large Scale Integr. (VLSI) Syst, vol. 24, no. 3, pp. 1203-1207 March 2016. [10] F. Kuttner, 'A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS,' 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), San Francisco, CA, USA, 2002, pp. 176-177 vol.1. [11] C. C. Liu et al., 'A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,' 2010 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, 2010, pp. 386-387. [12] C. C. Liu, '27.4 A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS,' 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 462-463. [13] W.-H. Tseng, et al., “A 12 bit 104MS/s SAR ADC in 28nm CMOS for Digitally-Assisted Wireless Transmitters,” IEEE ASSCC Dig. Tech. Papers, pp. 1-4, Nov. 2015. [14] S.-E. Chen and C.-C. Hsieh, “A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with Semi-Resting DAC,” in IEEE Symp. VLSI Circuits Dig., Jun. 2016, pp. 1-2. [15] G.-Y. Huang, et al., “A 1-uW 10-bit 200-kS SAR ADC with a Bypass Window for Biomedical Applications,” IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2783-2795, Nov. 2012. [16] B. P. Ginsburg and A. P. Chandrakasan, 'An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,' 2005 IEEE International Symposium on Circuits and Systems, 2005, pp. 184-187 Vol. 1. [17] C.-C. Liu, et al., “A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. [18] Yan Zhu, et al., “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010. [19] B. Wicht, et al., “Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, July 2004 [20] M. V. Elzakker, et al., “A 10-bit Charge Redistribution ADC Consuming 1.9uW at 1 MS/s,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. [21] T. Sepke, et al., “Noise Analysis for Comparator-Based Circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 3, pp. 541–553, March 2009. [22] Michael Choi and Asad A. Abidi, “A 6-b 1.3Gsample/s A/D Converter in 0.35-um CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 12, Dec. 2001. [23] S. H. Lewis, et al., “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351–358, March 1992. [24] C.-J. Tseng, et al., “A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling with Background Sampling-Point Calibration,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 10, pp. 2805-2815, Oct. 2014. [25] C.-C. Liu, et al., “A 10-bit 320-MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20-nm CMOS,” in IEEE ASSCC Dig. Tech. Paper, Nov. 2014, pp. 77–80. [26] P.-C. Huang, et al., “An 8-bit 900MS/s Two-Step SAR ADC,” in Proc. IEEE ISCAS, May 2016, pp. 2898-2898. [27] A. Chang, H. Lee and D. Boning, “A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration,” IEEE ESSCIRC, pp. 109-112, Sept. 2013. [28] C. C. Lee, C.-Y. Lu, R. Narayanaswamy, and J. B. Rizk, “A 12b 70 MS/s SAR ADC with digital startup calibration in 14 nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2015, pp. C62-C63. [29] W.-H. Tseng, et al., “A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters,” IEEE J. Solid-State Circuits, vol. 51, no. 10, Oct. 2016. [30] J.-H. Shen, et al., “A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS,” IEEE J. Solid-State Circuits, vol. PP, no. 99, pp. 1-12, Jan. 2018. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70073 | - |
| dc.description.abstract | 類比數位轉換器可以把自然訊號轉換成數位的格式，且可以應於於許多數位訊號處理器系統，例如：智慧型手機、電腦，本論文提出了一個操作於0.7伏特每秒一百萬次取樣的十二位元連續漸進式類比數位轉換器，實現在40奈米製程。
我們使用次區間的架構來提高速度與降低能量消耗，為了減少電容陣列切換的能量消耗，偵測與迴避演算法與同步切換技巧被採用，使用追蹤平均技巧來降低比較器設計的負擔，藉由校正，我們可以讓類比數位轉換器在使用較小的電容情況下又能維持良好的規格。 本次區間連續漸進式類比數位轉換器在每秒一百萬次的取樣速度與奈奎斯特的輸入頻率之下有十點七五的有效位元，其有效面積只占0.0198mm2，功率消耗為2.47uW，以FOMW表示為每步階轉換消耗1.43 fJ/conversion-step，此類比數位轉換器適合用在低功耗的手持、穿戴、與醫療等裝置。 | zh_TW |
| dc.description.abstract | An analog-to-digital converter (ADC) transforming natural signals to digital form can be used for many digital signal processor (DSP) applications such as smartphone and computer. A 0.7V 12-bit 1MS/s ADC fabricated in 40nm CMOS is proposed in the thesis.
The subranging architecture is used for improvement of speed and power. The detect-and-skip (DAS) algorithm and aligned switching method are adopted to reduce the switching energy of the DAC. To relax the noise design of comparator, tracking average is applied. With proposed capacitor calibration, we can use 0.5fF unit capacitor without affecting the performance of the ADC. The subranging SAR ADC achieves an ENOB of 10.75 at 1MS/s sampling rate with Nyquist input frequency. The active area is only 0.0198 mm2. It consumes 2.47uW and FoMw of 1.43fJ/conversion-step. It is suitable for portable, wearable and biomedical devices with low power consumption. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T03:42:02Z (GMT). No. of bitstreams: 1 ntu-107-R04943038-1.pdf: 2291158 bytes, checksum: 78bdc1a105be57e531382d5719f9a51e (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | Contents
致謝 I 摘要 II Abstract III List of Figures VI List of Tables VIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converter 3 2.1 Introduction 3 2.2 Static Performance 3 2.2.1 Offset Error 3 2.2.2 Gain Error 4 2.2.3 Differential Nonlinearity and Integral Nonlinearity (DNL and INL) 5 2.3 Dynamic Performance 6 2.3.1 Signal-to-Noise Ratio (SNR) 6 2.3.2 Total Harmonic Distortion (THD) 7 2.3.3 Spurious Free Dynamic Range (SFDR) 7 2.3.4 Signal to Noise and Distortion Ratio (SNDR) 8 2.3.5 Effective Number of Bits (ENOB) 8 2.3.6 Figure of Merit (FOM) 8 2.4 ADC Architectures 9 2.4.1 Successive-Approximation-Register 9 2.4.2 Time-Interleaved 11 2.4.3 Two-Step and Subranging Architecture 11 Chapter 3 Low-Power and High-Resolution SAR ADC Design 13 3.1 Introduction 13 3.1.1 Asynchronous SAR ADC 13 3.1.2 Design Consideration of SAR ADC 15 3.2 Capacitive-DAC Design 16 3.2.1 Settling Time 17 3.2.2 Sampling Noise 19 3.2.3 Capacitor mismatch 20 3.2.4 Switching Methods with Average Switching Energy 22 3.3 Comparator 23 3.3.1 Time-Domain Transient waves 24 3.3.2 Kickback Noise 26 3.3.3 Offset and Noise 27 3.4 Summary 33 Chapter 4 A High Resolution Sub-ranging SAR ADC with Weight Compensation Using Digital Calibration 34 4.1 Introduction 34 4.2 Proposed Architecture 35 4.3 SNR Enhancement Technique and Capacitor Switching Algorithm 37 4.3.1 Tracking average 38 4.3.2 Aligned Switching Technique 39 4.3.3 Detect-and-Skip Algorithm 42 4.4 Proposed Calibration 47 4.4.1 Cap Mismatch Quantization and Consideration 48 4.4.2 Weight-Split Compensation (WSC) 52 4.5 Circuit Implementation 54 4.5.1 Comparator 54 4.5.2 SAR Logic 58 Chapter 5 Experiment Results 61 5.1 Measurement Setup 61 5.2 Measurement Results 62 Chapter 6 Conclusions 68 Bibliography 69 | |
| dc.language.iso | en | |
| dc.title | 低功耗及高解析之數位校正連續漸進式類比數位轉換器 | zh_TW |
| dc.title | Power-Efficient and High-Resolution Successive-approximation Register Analog-to-Digital Converter with Digital Calibration | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),劉宗德(Tsung-Te Liu) | |
| dc.subject.keyword | 連續漸進式,類比數位轉換器,偵測和迴避,校正,追蹤平均, | zh_TW |
| dc.subject.keyword | Successive-approximation register (SAR),analog-to-digital converter (ADC),detect-and-skip (DAS),weight-split compensation (WSC),Vcm based switching,tracking average, | en |
| dc.relation.page | 73 | |
| dc.identifier.doi | 10.6342/NTU201800342 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-02-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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