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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70072完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
| dc.contributor.author | Yassin Yazal | en |
| dc.contributor.author | 沈亞信 | zh_TW |
| dc.date.accessioned | 2021-06-17T03:41:59Z | - |
| dc.date.available | 2021-02-23 | |
| dc.date.copyright | 2018-02-23 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-02-06 | |
| dc.identifier.citation | [1] R. K. Ahuja, T. L. Magnanti, and J. B. Orlin, Network Flows: Theory, Algorithms, and Applications. Prentice Hall, 1993.
[2] T. Cormen, C. Leiserson, R. Rivest, and C. Stein, Introduction to Algorithms. MIT press, 2009. [3] J.-W. Fang and Y.-W. Chang, “Area-I/O flip-chip routing for chip-package co-design,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 518-522, November 2008. [4] J.-W. Fang and Y.-W. Chang, “Area-I/O flip-chip routing for chip-package co-design considering signal skews,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 5, pp. 711-721, May 2010. [5] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An integer linear programming based routing algorithm for flip-chip design,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 606-611, June 2007. [6] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An integer-linear-programming-based routing algorithm for flip-chip designs,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 98-110, January 2009. [7] J.-W. Fang, Y.-W. C. I.-J. Lin, P.-H. Yuh, and J.-H. Wang, “A routing algorithm for flip-chip design,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 753-758, November 2005. [8] J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang, “A network-ow-based RDL routing algorithmz for flip-chip design,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1417-1429, August 2007. [9] J.-W. Fang, M. D. F. Wong, and Y.-W. Chang, “Flip-chip routing with unified area-I/O pad assignments for package-board co-design,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 336-339, July 2009. [10] M. R. Garey and D. S. Johnson, A Guide to the Theory of NP-Completeness, 1979. [11] Y.-K. Ho, H.-C. Lee, W. Lee, Y.-W. Chang, C.-F. Chang, I.-J. Lin, and C.-F. Shen, “Obstacle-avoiding free-assignment routing for flip-chip designs,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 2, pp. 224-236, February 2014. [12] J. H. Lau, “Overview and outlook of three-dimensional integrated circuit packaging, three-dimensional si integration, and three-dimensional integrated circuit integration,' Journal of Electronic Packaging, pp. 1-15, October 2014. [13] H.-C. Lee, Y.-W. Chang, and P.-W. Lee, “Recent research development in flip-chip routing,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 404-410, November 2010. [14] P.-W. Lee, C.-W. Lin, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, “An efficient pre-assignment routing algorithm for flip-chip designs,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 239-244, November 2009. [15] P.-W. Lee, H.-C. Lee, Y.-K. Ho, Y.-W. Chang, C.-F. Chang, I.-J. Lin, and C.-F. Shen, “Obstacle-avoiding free-assignment routing for flip-chip designs,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 1088-1093, November 2012. [16] Z. Li, Y. Li, and J. Xie, “Design and package technology development of face-to-face die stacking as a low cost alternative for 3D IC integration,' in Proceedings of IEEE Electronic Components and Technology Conference, pp. 338-341, May 2014. [17] B.-Q. Lin, T.-C. Lin, and Y.-W. Chang, “Redistribution layer routing for integrated fan-out wafer-level chip-scale packages,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 23-31, November 2016. [18] C.-W. Lin, P.-W. Lee, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, “An efficient pre-assignment routing algorithm for flip-chip designs,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 6, pp. 878-889, June 2012. [19] T.-C. Lin, C.-C. Chi, and Y.-W. Chang, “Redistribution layer routing for wafer-level integrated fan-out package-on-packages,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, November 2017. [20] X. Liu, Y. Zhang, G. K. Yeap, and C. Chu, “Global routing and track assignment for flip-chip designs,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 90-93, June 2010. [21] P. Pulici, G. P. Vanalli, M. A. Dellutri, D. Guarnaccia, F. L. Iacono, G. Campardo, and G. Ripamonti, “Signal integrity flow for system-in-package and package-on-package devices,' Proceedings of the IEEE, vol. 97, no. 1, pp. 84-95, January 2009. [22] K. J. Supowit, “Finding a maximum planar subset of a set of nets in a channel,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, no. 1, pp. 93-94, January 1987. [23] J. T. Yan and Z. W. Chen, “IO connection assignment and RDL routing for flip-chip designs,' in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 588-593, January 2009. [24] J. T. Yan and Z. W. Chen, “RDL pre-assignment routing for flip-chip design,' in Proceedings of the Great Lakes Symposium on VLSI, pp. 401-404, May 2009. [25] J. T. Yan and Z. W. Chen, “Pre-assignment RDL routing via extraction of maximal net sequence,' in Proceedings of IEEE International Conference on Computer Design, pp. 65-70, October 2011. [26] T. Yan and M. D. F.Wong, “Correctly modeling the diagonal capacity in escape routing,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 285-293, February 2012. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70072 | - |
| dc.description.abstract | 三維面對面封裝 (three-dimensional face-to-face package) 是一個大有可為的立體封裝技術，此封裝技術通常會包含一個下層封裝採用三維面對面封裝技術和一個上層封裝面對面堆疊。與傳統的封裝堆疊不同之處在於，三維面對面封裝有上層母封裝和下層子封裝兩個多層重分佈層 (redistribution layer) 面對面堆疊來進行訊號傳輸。據我們所知，目前尚未有發表的論文是針對處裡三維面對面封裝堆疊中的重分佈層繞線問題。大部分相關的發表論文著重於三種類型的重分佈層繞線問題，分別是自由配對繞線問題、非自由配對繞線問題與混合型配對繞線問題，並且考慮單一或是多個晶片。在此篇論文當中，我們提出了一個新的三維面對面封裝堆疊中的重分佈層繞線問題。為了彌補相關論文缺乏對於上層母封裝和下層子封裝兩個多層重分佈層的考慮，我們提出了第一個演算法來針對處理三維面對面封裝堆疊中的重分佈層繞線問題，此問題考慮到了訊號線的分層、重分佈層數量的最小化與總線長的最小化。我們提出了一個整數線性規劃繞線 (integer linear programming) 的演算法，這個演算法會針對這個問題保證找到最佳解。這裡會套用縮減技術來刪除重複的解答提升整體的運算速度，然後在不影響整個解答品質的前提下完成全區域的上下層繞線。實驗結果顯示我們的繞線器可以達到百分之百的繞線率並達到總線長的最小化且減少相對的運算時間在所有設計限制情況下，相較之下，相關發表論文所延伸的演算法得到的運算時間及限制變量數會得到較差的結果。 | zh_TW |
| dc.description.abstract | The three-dimensional (3D) face-to-face package is a promising 3D packaging technology, which consists of a top package stacked on a bottom package. The main difference between the face-to-face package and the traditional 3D package is that a 3D face-to-face package has a top package (mother chip) cover on the top of the bottom package (daughter chip) without using through-silicon vias (TSVs) to connect between them. The 3D face-to-face package flips the daughter chip to connect to the mother chip to increase the signal speed and reduce the factory cost. To the best of our knowledge, there is still no previous work specifically tackling redistribution layer (RDL) routing for the 3D face-to-face structure. Previous works on RDL routing mainly dealing with the 3D packages include top and bottom packages using TSVs, and they deal with unified-assignment routing for the multi-package problem. In this thesis, we formulated a new RDL routing problem for the 3D face-to-face structure, and we present the first routing algorithm in the literature to handle the unified-assignment RDL routing problem of 3D face-to-face structure. Our algorithm is based on integer linear programming and guarantees to find an optimal solution for addressing the problem. We use a reduction technique to prune redundant solutions, and create global routing paths between the bottom package and top package without loss of solution optimality. Finally, a detailed routing is applied to complete the routing. Experimental results show that our router can achieve 100% routability, optimal global-routing wirelength, and satisfy all constraints under reasonable runtime. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T03:41:59Z (GMT). No. of bitstreams: 1 ntu-107-R04921099-1.pdf: 1753714 bytes, checksum: 48c50f2c007be1c3cb94b2b948e70a82 (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | Acknowledgements iii
Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1Three-Dimensional Face-to-Face Packages 1 1.2Redistribution Layer Routing for Classical Flip-Chip Packages 8 1.3Related Work 10 1.3.1The Free-Assignment RDL Routing Problem 10 1.3.1.1 Network-Flow-Based Techniques 10 1.3.1.2 Non-Network-Flow-Based Techniques 13 1.3.2 The Pre-Assignment RDL Routing Problem 14 1.3.2.1 ILP-Based Techniques 14 1.3.2.2 Non-ILP-Based Techniques 14 1.3.3 The Unified-Assignment RDL Routing Problem 15 1.3.4 Integrated Fan-Out Packages RDL Routing Problem 16 1.4 Motivation 19 1.5 Our Contributions 22 1.6 Thesis Organization 22 Chapter 2. Preliminaries 23 2.1 Problem Formulation 23 2.2 Routing Design Rules 28 Chapter 3. Our Algorithm 30 3.1 Algorithm Overview 30 3.2 RDL Routing 32 3.2.1 ILP Formulation 33 3.2.2 ILP Reduction 37 3.2.3 Detailed Routing 38 Chapter 4. Experimental Results 42 4.1 Experimental Setup 42 4.2 Comparison and Analysis 43 Chapter 5. Conclusions and Future Work 49 Bibliography 53 | |
| dc.language.iso | en | |
| dc.subject | 三維面對面封裝 | zh_TW |
| dc.subject | 實體設計 | zh_TW |
| dc.subject | 重分佈層 | zh_TW |
| dc.subject | 重分佈層繞線 | zh_TW |
| dc.subject | Physical Design | en |
| dc.subject | Three-Dimensional Face-to-Face | en |
| dc.subject | Redistribution Layer | en |
| dc.subject | RDL Routing | en |
| dc.title | 三維面對面封裝之整數線性規劃繞線演算法 | zh_TW |
| dc.title | An Integer-Linear-Programming-Based Routing Algorithm for Three-Dimensional Face-to-Face Packages | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 江蕙如(Hui-Ru Jiang),方劭云(Shao-Yun Fang),黃婷婷(Ting-Ting Hwang) | |
| dc.subject.keyword | 實體設計,三維面對面封裝,重分佈層,重分佈層繞線, | zh_TW |
| dc.subject.keyword | Physical Design,Three-Dimensional Face-to-Face,Redistribution Layer,RDL Routing, | en |
| dc.relation.page | 56 | |
| dc.identifier.doi | 10.6342/NTU201800345 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-02-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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