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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/69531完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
| dc.contributor.author | Hung-Yu Chen | en |
| dc.contributor.author | 陳虹宇 | zh_TW |
| dc.date.accessioned | 2021-06-17T03:18:24Z | - |
| dc.date.available | 2028-06-28 | |
| dc.date.copyright | 2018-07-03 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-06-28 | |
| dc.identifier.citation | References
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/69531 | - |
| dc.description.abstract | 本論文中研究了具環繞金氧半(P型)閘極穿隧二極體，在第一章中簡述了金氧半結構的背景，包括先前研究過的飽和電流、陽極氧化製程、以及氧化層厚度的計算。接著在第二章中，光學應用中的光檢測體參考先前施加的閘極偏壓條件，透過氧化層厚度的調變加以研究，提出由厚氧化層提高靈敏度。在接下來的三個章節：第三章、第四章、第五章，對於低功率元件條件下，各種閘極寬度(5,10,15,20um)的討論及其應用進行研究。在第三章中，採用閘極接地時，二極體的飽和電流在薄氧化層元件隨閘極寬度而增加，在厚氧化層元件時則反之減小。此外，對於第四章中閘極斷路情況下，僅當氧化層厚度為2.5 nm時，二極體電流隨閘極寬度而減小。對於氧化層厚度2.1nm及2.8nm的元件，二極體電流幾乎與閘極寬度無關，且發現讀取的閘極電壓在浮閘時，會隨氧化層厚度而變化。然後在第五章中，對於電晶體特性的應用，窄閘極幫助次臨界擺幅大幅減少，而且在厚氧化層元件中的窄閘極表現出更高的光靈敏度。 最後，第六章是本文的結論和未來的研究方向建議。 | zh_TW |
| dc.description.abstract | In this dissertation, the studies of tunneling diode with surrounding MIS (p) gate was presented. The back ground of MIS structure, including the previous studies of saturation current, anodization process, and calculation of oxide thickness, was described in Chapter 1. Next, in chapter 2, optical application of photodetector, based on previous biased gate condition, was studied with the modulation of oxide thickness. It was suggested that higher sensitivity was obtained by thicker oxide. In following three chapters, i.e., Chapter 3, Chapter 4, and Chapter5, the discussions of various gate widths of 5, 10, 15, 20 um with low-power device consideration and its applications were studied. In Chapter 3, while adopting ground gate bias, diode current at saturation region increases with gate width for thinner oxide, but decreases for thicker oxide. In addition, for open gate condition in Chapter 4, diode current decreases with gate width only for oxide thickness of 2.5 nm. Diode currents are almost independent of gate width for oxide thickness of 2.1 nm 2.8 nm. Also, the read voltage varies with oxide thickness as gate biased at floating condition. Subsequently, in Chapter 5, for application of advanced transistor, narrow gate helps S.S. to decrease efficiently. Also, narrow gate device illustrates higher sensitivity with thicker oxide. Finally, the conclusion of this dissertation and the suggested future work are given in Chapter 6. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T03:18:24Z (GMT). No. of bitstreams: 1 ntu-107-R05943076-1.pdf: 3102673 bytes, checksum: 5c911f470ff3ef540a7c51348a149265 (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 摘要 I
Abstract II Contents III Figure caption V Chapter 1: Introduction 1 1.1. Motivation 1 1.2. Fundamental MIS(p) tunnel diode characteristic 2 1.3. Anodization process for thin oxide 7 1.4. Determination of oxide thickness 10 Chapter 2: Oxide thickness modulation for MIS(P) with surrounding gate and its application 16 2.1. Introduction 16 2.2. Experimental 17 2.3. Result and discussion 19 2.4. Conclusion 25 Chapter 3: Effect of surrounding gate width when ground condition 26 3.1. Introduction: 26 3.2. Experimental details 27 3.3. Result and Discussion 28 3.4. Conclusion 38 Chapter 4: Effect of surrounding gate width when open floating and open condition 39 4.1. Introduction 39 4.2. Experimental 39 4.3. Result and discussion 39 4.4. Conclusion 46 Chapter 5: Effect of gate width on devices sensitivity 47 5.1. Introduction 47 5.2. Experimental 48 5.3. Result and Discussion 49 5.3.1. Transistor characteristics 49 5.3.2. Photo sensitivity 58 5.4. Conclusion 63 Chapter 6: Conclusion and Future work 64 6.1. Conclusions 64 6.2. Suggestions for Future Work 65 References 67 | |
| dc.language.iso | en | |
| dc.subject | 金氧半電容 | zh_TW |
| dc.subject | 超薄氧化層 | zh_TW |
| dc.subject | 穿隧二極體 | zh_TW |
| dc.subject | ultrathin oxide | en |
| dc.subject | MOS | en |
| dc.subject | tunneling diode | en |
| dc.title | 具環繞閘金氧半穿隧二極體結構之研究 | zh_TW |
| dc.title | Study of MIS(p) Tunneling Diode Structures with Surrounding MIS(P) Gate | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 鄭晃忠(Huang-Chung Cheng),林浩雄(Hao-Hsiung Lin) | |
| dc.subject.keyword | 金氧半電容,穿隧二極體,超薄氧化層, | zh_TW |
| dc.subject.keyword | MOS,tunneling diode,ultrathin oxide, | en |
| dc.relation.page | 69 | |
| dc.identifier.doi | 10.6342/NTU201801188 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-06-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-107-1.pdf 未授權公開取用 | 3.03 MB | Adobe PDF |
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