使用多重臨界電壓互補式金氧半導體技術考慮電路架構與元件價值節省單晶片系統靜態功率方法

Abstract

本論文主要在探討應用多重臨界電壓互補式金氧半導體(MTCMOS)技術並且考慮電路架構與元件價值來降低單晶片系統靜態功率消耗的演算法。MTCMOS標準元件一般可分為兩種不同的臨界電壓，分別是高臨界電壓與標準臨界電壓。臨界電壓值較高的高臨界電壓元件能夠產生較低的靜態功率，而臨界電壓值較低的標準臨界電壓元件則有速度較快的優點。結合兩種臨界電壓元件的優點，使用演算法讓數位電路中的元件是由混和高臨界電壓與標準臨界電壓元件建立而成，讓數位電路能夠快速且產生較低的靜態功率，得到效能較好的數位電路。 本論文將提出三種應用MTCMOS技術的演算法，並使用64位元乘法器來驗證演算法執行效果。第二章引用了GDSPOM演算法，分析演算法的優劣，提出比GDSPOM多降低約4%至6%靜態功率的GDSPOMWV演算法。第三章引用了CBLPRP演算法，提出比CBLPRP多降低3%至6%靜態功率的CBSPRM演算法。第四章結合了第二章與第三章提出的演算法GDSPOMWV與CBSPRM，提出降低靜態功率效果更好的演算法CACVPOM。比GDSPOMWV多節省11%至14%靜態功率，也比CBSPRM多節省了1%至2%靜態功率。 本論文提出的三個演算法，都考慮了電路架構影響與元件本身價值的影響，讓電路以MTCMOS技術來建立時，能夠降低更多的靜態功率，得到更好的執行效果。

This thesis presents an improved algorithm to reduce static power for SOC considering circuit architecture using MTCMOS technology, using a high threshold voltage cell for low power and a low threshold voltage cell for high speed. The algorithm reported in this thesis helps mix multiple threshold voltage cells in SOC circuits, making the digital circuits perform better. In this thesis, three algorithms using MTCMOS technology were proposed. A 64-bit multiplier is used as a test vehicle to verify performance of the algorithms. In Chapter 2, the algorithm GDSPOMWV derived from GDSPOM is proposed. Via GDSPOMWV, the SOC chip multiplier can reduce about 4% to 6% static power as compared to the GDSPOM. Chapter 3 proposes another algorithm CBSPRM derived from CBLPRP. Via CBSPRM, the SOC may reduce about 3% to 6% static power as compared to the CBLPRP. In Chapter 4, combining the idea of the algorithm GDSPOMWV with CBSPRM, the algorithm CACVPOM is proposed, which can reduce about 11% to 14% static power as compared to GDSPOMWV. It can reduce about 1% to 2% static power as compared to CBSPRM.