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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭斯彥 | |
dc.contributor.author | Chien Yu | en |
dc.contributor.author | 游謙 | zh_TW |
dc.date.accessioned | 2021-06-17T03:09:44Z | - |
dc.date.available | 2018-08-06 | |
dc.date.copyright | 2018-08-06 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018-07-20 | |
dc.identifier.citation | [1] S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa and I. L. Markov, “Unification of partitioning, placement and floorplanning,” IEEE/ACM International Conference on Computer Aided Design, pp. 550-557, 2004.
[2] Sergey Babin, Sergey Borisov, Vladimir Militsin, Elena Patyukova, “Simulation and correction of resist charging due to fogging in electron-beam lithography”, Proc. SPIE, Photomask Technology, p. 888019, October 2013. [3] Sergey Babin, Sergey Borisov, Elena Patyukova, “Dose variation and charging due to fogging in electron beam lithography: simulations using CHARIOT Monte Carlo software”, Proc. SPIE, European Mask and Lithography Conference, p. 88860E, October 2013. [4] Tai-Chen Chen, Yao-Wen Chang and Shyh-Chang Lin, “A novel framework for multilevel full-chip gridless routing,” Asia and South Pacific Conference on Design Automation, pp. 636-641, 2006. [5] Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, L. Chen and B. Han, “Novel full-chip gridless routing considering double-via insertion,” ACM/IEEE Design Automation Conference, San Francisco, CA, pp. 755-760, 2006. [6] Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang and Sheng-Lung Wang, “Novel wire density driven full-chip routing for CMP variation control,” IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 831-838, 2007. [7] J. Cong, Jie Fang, Min Xie and Yan Zhang, “MARS-a multilevel full-chip gridless routing system,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 382-394, March 2005. [8] Yao-Wen Chang and Shih-Ping Lin, “MR: a new framework for multilevel full-chip routing,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 793-800, May 2004. [9] Cooley, James W., and John W. Tukey. “An Algorithm for the Machine Calculation of Complex Fourier Series.” Mathematics of Computation, vol. 19, no. 90, pp. 297–301, 1965. [10] A. Fujimura, “Beyond light: The growing importance of E-beam,” in Processing Tutorial International Conference Computer-Aided Design, November 2009. [11] A. Fujimura, “Design for E-beam: Getting the best wafers without the exploding mask costs,” in Processing Keynote International Symposium Quality Electronic Design, March 2010. [12] Thiago Figueiro, Clyde Browning, Martin J. Thornton, Cyril Vannufel, Patrick Schiavone, “Reticle level compensation for long range effects”, Proc. SPIE, Alternative Lithographic Technologies V, p. 868028, March 2013. [13] Thiago Figueiro, Clyde Browning, Martin J. Thornton, Cyril Vannuffel, Kang-Hoon Choi, Christoph Hohle, Jean-Herve Tortai, Patrick Schiavone, “Extreme long range process effects characterization and compensation”, Proc. SPIE, European Mask and Lithography Conference, p. 88860F, October 2013. [14] Peter Hudek, Ulrich Denker, Dirk Beyer, Nikola Belic, Hans Eisenmann, “Fogging effect correction method in high-resolution electron beam lithography”, Microelectronic Engineering, vol. 84, no. 5–8, pp. 814-817, 2007. [15] Yu-Chen Huang and Y. W. Chang, “Fogging effect aware placement in electron beam lithography,” ACM/EDAC/IEEE Design Automation Conference, Austin, TX, pp. 1-6, 2017. [16] J. ichi Kon, Y. Kojima, Y. Takahashi, T. Maruyama, and S. Sugatani, “Characterization of fogging and develop-loading effects in electron-beam direct-writing technology,” Japanese Journal of Applied Physics, vol. 51, no. 6S, p. 06FC04, June 2012. [17] R. F. W. Pease, “Electron beam lithography,” Contemporary Physics, vol. 22, no. 3, pp. 265-290, 1981. [18] Linda K. Sundberg, Greg M. Wallraff, Alexander M. Friz, Blake Davis, Amy E. Zweber, Robert Lovchik, Emmanuel Delamarche, Tasuku Senna, Toru Komizo, William D. Hinsberg, “Two complementary methods to characterize long range proximity effects due to develop loading”, Proc. SPIE, Photomask Technology, p. 78230G, September 2010. [19] P. Saxena, R. S. Shelar, and S. S. Sapatnekar, Routing congestion in VLSI circuits: estimation and optimization, Spring, New York, USA, 2007. [20] Naoharu Shimomura, Munehiro Ogasawara, Jun Takamatsu, Shusuke Yoshitake, Kenji Ooki, Noriaki Nakayamada, Fumiyuki Okabe, Toru Tojo, “Reduction of fogging effect caused by scattered electrons in an electron beam system”, Proc. SPIE, Photomask and X-Ray Mask Technology VI, August 1999. [21] A. A. Tseng, K. Chen, C. D. Chen, and K. J. Ma, “Electron beam lithography in nanoscale fabrication: Recent development”, IEEE Transactions on Electronics Packaging Manufacturing, vol. 26, no. 2, pp. 141-149, April 2003. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/69149 | - |
dc.description.abstract | 電子束微影為具發展性之下世代微影技術中的一項,用以克服傳統光學微影的解析度限制。然而,電子束微影要實際應用於量產製作仍然存在挑戰。其中一項是霧化效應,它是阻劑和基質中的再散射電子所引起的,在毫米級的範圍造成多餘的曝光。霧化效應導致線端失真和關鍵尺寸的不一致性,其與電路圖樣密度有密切關係,過去的研究在電路擺置階段修正霧化效應。電路擺置結束後,在電路繞線階段,導線密度相當於圖樣密度。因此,透過導線連接的佈置,我們可以控制霧化效應。本論文提出了一種考慮電子束霧化效應的繞線演算法,以盡量減少霧化效應的變化。我們提出了一個新的觀點用以抵消霧化效應。實驗結果顯示我們的演算法可以減少霧化效應的變化,甚至改善執行時間。 | zh_TW |
dc.description.abstract | Electron beam lithography (EBL) is one promising candidates among next-generation lithography (NGL) technology to conquer the resolution limit of the optical lithography. However, there are still challenges for EBL to apply practically in massive production. One of those obstacles is the fogging effect. It caused by re-scattered electrons in the resist and the substrate.
Increases the undesired exposure in a wide range up to millimeter scale. As a result, the fogging effect gives rise to line end distortion and the non-uniformity of critical dimension (CD). The pattern distribution is highly related to the fogging effect. A previous work tackles the fogging effect in the placement stage. In the routing stage, pattern density is equivalent to the wire density. As routing follows closely after placement stage. Thus, by arranging the positions of net connections, we can control the result of the fogging effect. In this thesis, we present a routing algorithm considering e-beam fogging effect to minimize the variation of the fogging effect. A new point of view has proposed to offset the fogging effect. Experimental results show that our algorithm can reduce the fogging effect variation even improving the runtime. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T03:09:44Z (GMT). No. of bitstreams: 1 ntu-107-R03943141-1.pdf: 839066 bytes, checksum: 73ce9193bd922e73c96d6cec1cf5e326 (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | Acknowledgements i
摘要ii Abstract iii 1 Introduction 5 1.1 Electron Beam Lithography . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.1 Fogging Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 Energy Distribution Model . . . . . . . . . . . . . . . . . . . . . 7 1.1.3 Fogging Effect Evaluation . . . . . . . . . . . . . . . . . . . . . 8 1.2 VLSI Circuit Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.1 Global Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.2 Detailed Routing . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.1 Fogging Effect Correction in Manufacturing Process . . . . . . . 11 1.3.2 Fogging Effect Correction in Design Stage . . . . . . . . . . . . 11 1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.6 Thesis Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Preliminaries 14 2.1 Multilevel Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.1 Convolution and Deconvolution . . . . . . . . . . . . . . . . . . 16 2.2.2 Computation Complexity . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Routing Considering Fogging Effect 20 3.1 Algorithm Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 Routing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 Fogging Critical Area Analysis . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Fogging Effect Aware Global Routing . . . . . . . . . . . . . . . . . . . 22 4 Experimental Results 24 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 Conclusions and Future Work 28 Bibliography 29 | |
dc.language.iso | en | |
dc.title | 電子束微影霧化效應感知多級電路繞線 | zh_TW |
dc.title | Fogging Effect Aware Multilevel Routing in Electron Beam Lithography | en |
dc.type | Thesis | |
dc.date.schoolyear | 106-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 顏嗣鈞,陳英一,雷欽隆,袁世一 | |
dc.subject.keyword | 實體設計,電子束微影,霧化效應,可製造性,電路繞線, | zh_TW |
dc.subject.keyword | Physical Design,Electron Beam Lithography,Fogging Effect,Manufacturability,Routing, | en |
dc.relation.page | 31 | |
dc.identifier.doi | 10.6342/NTU201801296 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2018-07-23 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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