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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Yi-An Lee | en |
dc.contributor.author | 李翼安 | zh_TW |
dc.date.accessioned | 2021-06-17T02:43:49Z | - |
dc.date.available | 2020-08-24 | |
dc.date.copyright | 2017-08-24 | |
dc.date.issued | 2017 | |
dc.date.submitted | 2017-08-15 | |
dc.identifier.citation | [1] Chin-Khai Tang, Ming-Shing Su, and Yi-Chang Lu, “LineDiff Entropy: Lossless Layout Data Compression Scheme for Maskless Lithography Systems,” IEEE Signal Processing Letters, Vol. 20, No. 7, July 2013.
[2] P. Petric, C. Bevis, A. Brodie, A. Carroll, A. Cheung, L. Grella, M. McCord, H. Percy, K. Standiford, and M. Zywno, “REBL nanowriter: Reflective Electron Beam Lithography,” Proc. SPIE, vol. 7271, Alternative Lithographic Technologies, 727107, Mar. 2009. [3] Ming-Shing Sua, Kuen-Yu Tsaia, Yi-Chang Lua, Yu-Hsuan Kuoa, Ting-Hang Peia, and Jia-Yush Yenb, “Architecture for next generation massively parallel maskless lithography system (MPML2),” Proc. SPIE, Vol. 7637, Alternative Lithographic Technologies II, 76371Q, Apr. 2010. [4] V. Dai, “Data Compression for Maskless Lithography Systems: Architecture, Algorithms and Implementation,” Ph.D. dissertation, University of California, Dept. Electrical Engineering Computer Science, Berkeley, CA, USA, 2008. [5] Jeehong Yang, “Lossless Circuit Layout Image Compression Algorithm for Multiple Electron Beam Direct Write Lithography Systems,” Ph.D. dissertation, University of Michigan, 2012. [6] Yu-Hsiang Chiu, “Data Compression Ratio-aware Detailed Routing for Multiple E-Beam Direct Write Systems” Thesis of National Taiwan University, Sep. 2015. [7] Cheng-Chi Wu, Jensen Yang, Wen-Chuan Wang, Shy-Jay Lin, “An Instruction-based High-Throughput Lossless Decompression Algorithm for E-Beam Direct-Write System,” Proc. SPIE, vol. 9423, Alternative Lithographic Technologies VII, 94231P, Mar. 2015. [8] Jacob Ziv, Abraham Lempel, 'A Universal Algorithm for Sequential Data Compression'. IEEE Transaction on Information Theory, Vol. IT-23, No. 3, May 1977. [9] Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Cheng, “Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon),” 1st Edition, Elsevier Inc., 2009, Chapter 12. [10] Lee, C.Y., and Whippany, N. J., “An Algorithm for Path Connections and Its Applications,” IEEE IRE Transactions on Electronic Computers, Vol. EC-10, No. 3, Sept. 1961. [11] Peter E. Hart, Nils J. Nilsson, Bertram Raphael, “A Formal Basis for the Heuristic Determination of Minimum Cost Paths,” IEEE Transactions on Systems Science and Cybernetics, Vol. 4, No. 2, July, 1968. [12] Minsik Cho, Yongchan Ban, and David Z. Pan, “Double Patterning Technology Friendly Detailed Routing,” in IEEE/ACM International Conference on Computer-Aided Design, 2008, pp. 506 – 511. [13] Shao-Yun Fang, “Lithography Optimization for Sub-22 Nanometer Technologies,” Ph.D. dissertation, National Taiwan University, Graduate Institute of Electronics Engineering, Taipei, Taiwan, 2013. [14] Jhih-Rong Gao, and David Z. Pan, “Flexible self-aligned double patterning aware detailed routing with prescribed layout planning,” Proceedings of the ACM international symposium on International Symposium on Physical Design, 2012, pp. 25-32. [15] Soukup, J., “Fast Maze Router,” 15th Design Automation Conference, 1978, pp. 100-102. [16] Akers, Sheldon B., “A Modification of Lee’s Path Connection Algorithm,” IEEE Transactions on Electronic Computers, Vol. EC-16, No. 1, Feb., 1967. [17] 2013 International Technology Roadmap for Semiconductors: http://www.itrs.net/ [18] S.-Y. Lee and B. D. Cook, “PYRAMID-A Hierarchical, Rule-Based Approach Toward Proximity Effect Correction-Part I: Exposure Estimation,” IEEE Transactions on Semiconductor Manufacturing, Vol.11, No. 1, pp. 108-116, 1998. [19] Shy-Jay Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Jaw-Jung Shin, Burn J. Lin, ” Influence of Data Volume and EPC on Process Window in Massively Parallel E-Beam Direct Write,” Proc. SPIE, vol. 8680, Alternative Lithographic Technologies V, 86801C,March, 2013. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/68951 | - |
dc.description.abstract | 由於製程不斷演進,物理極限已成為超大型積體電路的最小關鍵尺寸的瓶頸,然而使用於傳統光學曝光的光源也因其解析度不足逐漸不敷使用,因此具備較低成本與高度精確等特性的電子束曝光成為極具潛力的次世代製程選擇。為了支援電子束的高度解析度,使用上必須仰賴龐大的資料將電路資訊傳輸至曝光系統。然而要在現今複雜程度與日俱增的超大型積體電路製程中達到預期的產率,就必須同步進行資料傳輸以及電子束機臺曝光顯影,因此在工業的使用上,會先將電路資訊壓縮後再傳輸至曝光系統,並在機臺上解壓縮,來突破資料傳輸的瓶頸。本篇論文將要探討的問題是,是否能夠在電路實體設計的階段中,優先考慮電路布局經過像素化的過程之後,產生出能讓壓縮演算法表現得更加優異的資料排列方式,並且針對這種特定的排列方式設計一個專門的壓縮方式,藉此達到提升壓縮效率的效果。 | zh_TW |
dc.description.abstract | Along with the advancement of technology, the feature size of Integrated Circuits(IC) are shrinking down day after day, but the resolution of the ArF laser is not enough to support next generation lithography. Electron beam lithography have a role to play in next generation lithography with its characteristic of high-accuracy. In order to support the accuracy of Electron beam, the massive data size of the circuit has to be delivered to the E-beam emitter. However, circuits nowadays have become more complicated. In order to synchronize the operation of Electron beam lithography with data transmission, the successfulness of this process relies on the speed of data transmission, which is not sufficiently fast even with technologies today. So in practice, the massive circuit data should be compressed before transmitted by optic fibers, and then decompressed on the chip of E-beam machines. In this thesis, considering the data arrangement after rasterization, we proposed a method to improve router. Besides, we modify data compression algorithm to support the particular arrangement of data. The results of experiments show that we not only improve data compression ratio with our proposed algorithms but establish a procedure of data transformation for multiple electron beam direct write systems. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T02:43:49Z (GMT). No. of bitstreams: 1 ntu-106-R04943081-1.pdf: 3537833 bytes, checksum: 182ca344a7288e21061bccd8a1f4013b (MD5) Previous issue date: 2017 | en |
dc.description.tableofcontents | 口試委員審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv CONTENTS v LIST OF FIGURES vii LIST OF TABLES ix Chapter 1 Introduction 1 1.1 MEBDW Systems Difficulty 2 1.2 Motivation and Accomplishment 5 1.3 Organization 6 Chapter 2 Preliminaries 7 2.1 MEBDW System Architecture Designs 7 2.2 Data Compression algorithms 8 2.2.1 Introduction of data compression algorithms 9 2.2.2 LineDiff Entropy 11 2.3 Routing Algorithms 14 2.3.1 A* search Algorithm 16 2.3.2 Data compression ratio-aware detailed routing [6] 18 Chapter 3 Proposed Techniques 26 3.1 Routing phase 26 3.1.1 4-layers routing 26 3.1.2 Symmetrical wires 28 3.2 Rasterization 29 3.2.1 Orientation 30 3.2.2 Folding algorithm 32 3.3 Compression algorithm of folded stripes 34 Chapter 4 Results of Experiments 38 Chapter 5 Conclusion and Future Work 53 REFERENCE 55 | |
dc.language.iso | en | |
dc.title | 應用於多電子束直寫系統之資料壓縮比例感知繞線 | zh_TW |
dc.title | Data Compression Ratio-aware Routing for Multiple E-Beam Direct Write Systems | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 江介宏,盧奕璋,鄭文豪,蔡坤諭 | |
dc.subject.keyword | 電子束曝光,資料壓縮,實體設計,電路布局,繞線, | zh_TW |
dc.subject.keyword | Lithography,Electron Beam,Data Compression Algorithm,Physical Design,Detailed Routing,Rasterization, | en |
dc.relation.page | 57 | |
dc.identifier.doi | 10.6342/NTU201703544 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2017-08-16 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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