微波與毫米波分佈式放大器及變壓器之電壓式功率結合技術之堆疊式功率放大器研究

Abstract

本論文將介紹製作於互補式金氧半電晶體(CMOS FET)製程之低功耗和小晶片面積的分佈式放大器，與具有大功率輸出能力和小晶片面積的功率放大器。 首先提出的是由180奈米互補式金氧半電晶體製程所設計之傳統分佈式放大器(CDA)為架構，並以單級分佈式放大器(CSSDA)為其中增益元件，再利用反饋變壓器以達到訊號耦合的效益。其中增益頻寬積(GBW product)，直流功耗和晶片面積為設計此分佈式放大器的考量。在利用反饋變壓器的情形下，此分佈式放大器可以在不影響特性表現的情況下，有降低直流功耗和達到縮小晶片面積的效果。此分佈式放大器可以達到12-dB的小訊號增益和33.5 GHz的頻寬(頻寬內增益變化大於3 dB)，且直流功耗僅有69 mW，而晶片總面積只有0.72平方毫米。 接著是設計於60 GHz 的堆疊式功率放大器(stacked-PA)，由65奈米互補式金屬氧化物半導體製程所實現，此設計中使用了變壓器之電壓式輸出結合器。此輸出結合器於60 GHz的操作頻率下只有0.9 dB之介入損耗及小的尺寸(0.02平方毫米)，以用來提供高功率結合。採用堆疊式的功率放大器以提高元件的供應電壓和輸出功率。此功率放大器於60 GHz 的操作頻率下達到了22.8 dBm的飽和功率輸出、15.9 %之最大功率附加效率，其中不包含輸出變壓器所提供的損耗，而晶片核心面積僅為0.28平方毫米。

This thesis presents a CMOS compact and low dc power distributed amplifier (DA) and a CMOS power amplifier (PA) with high output power and compact size. Firstly, the conventional distributed amplifier (CDA) with cascaded single-stage distributed amplifier (CSSDA) gain stage using the feedback transformer for signal-coupling purpose implemented in 0.18-μm CMOS is proposed. It takes considerations of gain-bandwidth (GBW) products, dc power consumption, and chip size. By using the feedback-transformer, this DA reduces dc power consumption and achieve a compact chip size while maintaining the gain and bandwidth performances. This DA achieves 12-dB gain and 33.5-GHz bandwidth, which the gain variation is over 3 dB, with total dc power of 69 mW and the compact size of 0.72 mm^2. Secondly, the 60-GHz stacked-power amplifier implemented in 65-nm CMOS is designed with transformer (TF)-based voltage-type output combiner. This output combiner with only 0.9-dB insertion loss at 60 GHz and 0.02- mm^2 compact size is designed for high output power combining. The stacked-PA topology is adopted for increasing the supply voltage to the devices and the output power of the PA. The proposed power amplifier achieves saturated output power (P_SAT) of 22.8 dBm with 15.9% 〖PAE〗_max at 60 GHz excluding the loss of the output transformer and the chip size is only 0.28 mm^2 excluding the pads.