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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林浩雄 | |
dc.contributor.author | Chien-Hong Teng | en |
dc.contributor.author | 鄧建鴻 | zh_TW |
dc.date.accessioned | 2021-06-17T01:29:56Z | - |
dc.date.available | 2017-08-08 | |
dc.date.copyright | 2017-08-08 | |
dc.date.issued | 2017 | |
dc.date.submitted | 2017-08-04 | |
dc.identifier.citation | Bibliography
[1] https://www.flickr.com/photos/jurvetson/31409423572/ [2] Takayasu Sakurai, “Perspectives of low power VLSI’s,” IEICE Trans. Electron, E87-C, pp. 429–436, 2004. [3] Adrian M. Ionescu and Heike Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” NATURE, vol. 479, pp. 329-337, 17 November 2011. [4] Qin. Zhang, Wei. Zhao, and Alan. Seabaugh, “Low-subthreshold-swing tunnel transistors,” IEEE Electron Device Letters, vol. 27, no. 4, pp. 297-300, 2006. [5] Hao. Lu and Alan. Seabaugh, “Tunnel field-effect transistors: state-of-the-art,” IEEE Journal of the Electron Devices Society, vol. 2, no. 4, pp. 44-49, 2014. [6] Sayeef. Salahuddin and Supriyo. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Letters, vol. 8, no. 2, pp. 405-410, 2008. [7] Asif. I. Khan, Chun. W. Yeung, Chenming. Hu, and Sayeef. Salahuddin, “Ferroelectric negative capacitance MOSFET: capacitance tuning & antiferroelectric operation,” International Electron Device Meeting (IEDM), no. 11.3, 2011. [8] Kai-Shin. Li, Pin-Guang. Chen, Tung-Yan. Lai, Chang-Hsien. Lin, Cheng-Chih. Cheng, Chun-Chi. Chen, Yun-Jie. Wei, Yun-Fang. Hou, Ming-Han. Liao, Min-Hung. Lee, Min-Cheng. Chen, Jia-Min. Sheih, Wen-Kuan. Yeh, Fu-Liang. Sayeef. Salahuddin, and Chenming. Hu, “Sub-60mV-swing negative-capacitance FinFET without hysteresis,” International Electron Device Meeting (IEDM), no. 22.6, 2015. [9] Ji-Hun Kim, Zack C.Y. Chen, Soonshin Kwon and Jie Xiang, “Steep Subthreshold Slope Nanoelectromechanical Field-Effect Transistors with Nanowire Channel and Back Gate Geometry,” Device Research Conference (DRC), pp. 209-210, 2013. [10] Woo Young Choi, Jae Young Song, Byung Yong Choi, Jong Duk Lee, Young June Park, and.Byung-Gook Park, “80nm Self-Aligned Complementary I-MOS Using Double Sidewall Spacer and Elevated Drain Structure and Its Applicability to Amplifiers with High Linearity,” International Electron Device Meeting (IEDM), no. 8.5, 2004. [11] Bill Holt, “Areas of Intel’s processing technology research,” Intel Investor Meeting, Nov. 19, 2015 SANTA CLARA. [12] Zener, Clarence. “A theory of electrical breakdown of solid dielectrics,” Proc. R. Soc. Lond. A 145, pp. 523–529, 1934. [13] Sze, Simon. M. Physics of Semiconductor Devices, 1st edn (John Wiley, 1969). [14] Quentin Smets, Anne S. Verhulst, Salim El Kazzi, Devin Verreck, Olivier Richard, Hugo Bender, Nadine Collaert, Anda Mocuta, Aaron Thean, and Marc M. Heyns, “Extracting the effective bandgap of heterojunctions using Esaki diode I-V measurements,” Applied Physics Letters, vol. 107, p. 072101, 2015. [15] https://nanoravi.wordpress.com/2011/02/10/multigate-soi-mosfets/ [16] Ran-Hong Yan, Abbas Ourmazd and Kwing F. Lee. “Scaling the Si MOSFET: From Bulk to SOI to Bulk” IEEE Transactions on electron devices, vol. 39, no. 7, July 1992 [17] Wei Wang, Peng-Fei Wang, Chun-Min Zhang, Xi Lin, Xiao-Yong Liu, Qing-Qing Sun, Peng Zhou, and David Wei Zhang, “Design of U-Shape Channel Tunnel FETs With SiGe Source Regions” IEEE Transactions on Electron Devices, vol. 61, no. 1, pp. 193-197, January 2014. [18] Sang Wan Kim, Jang Hyun Kim, Tsu-Jae King Liu, Woo Young Choi, and Byung-Gook Park, “Demonstration of L-Shaped Tunnel Field-Effect Transistors” IEEE Transactions on Electron Devices, vol. 63, no. 4, pp. 1774-1778, April 2016. [19] Zhaonian Yang, “Tunnel Field-Effect Transistor With an L-Shaped Gate” IEEE Electron Device Letters, vol. 37, no. 7, pp. 839-842, July 2016. [20] Sentaurus Device User Guide, Version G-2012.06. [21] https://service.nchc.org.tw/info/floating_desc.php [22] Thurber, Mattis, Liu, and Filliben, “The Relationship Between Resistivity and Dopant Density for Phosphorus-and Boron-Doped Silicon,” (May 1981) [23] Y B Li, I T Ferguson, R A Stradling and R Zallen. “Raman scattering by plasmon-phonon modes in highly doped n-InAs grown by molecular beam epitaxy” Semicond. Sci. Technol. 7 pp. 1149-1154, 1992. [24] CRC Handbook of Chemistry and Physics version 2008, p. 12–114. [25] Kian-HuiGoh, Kian-Hua Tan, Sachin Yadav, Annie, Soon-Fatt Yoon, Gengchiau Liang, Xiao Gong, and Yee-Chia Yeo1. “Gate-All-Around CMOS (InAs n-FET and GaSb p-FET) based on Vertically-Stacked Nanowires on a Si Platform, Enabled by Extremely-Thin Buffer Layer Technology and Common Gate Stack and Contact Modules” IEEE IEDM 15-394, pp. 15.4.1-15.4.4, 2015 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/67380 | - |
dc.description.abstract | 我們使用新思科技的Sentaurus TCAD軟體模擬砷化銦-矽異質接面環繞式閘極奈米線穿隧式場效應電晶體之電特性。結果顯示與矽同質接面相比砷化銦-矽異質接面有更大的導通電流,而與單閘極結構相比環繞式閘極結構有更好的次臨限斜率。原因為砷化銦-矽異質接面的穿隧能障比矽同質接面小而環繞式閘極結構的閘極控制力比單閘極結構好。此外,因為穿隧現象主要發生在奈米線表面所以奈米線的直徑對電晶體的特性影響不大。為了改善次臨限斜率特性,我們提出矽袖珍結構。此結構能夠藉由矽到矽的穿隧現象降低次臨限斜率。而為了提高導通電流,我們提出內核外殼結構。此結構能夠藉由增加發生穿隧現象的面積提高導通電流。不過因為側向的穿隧能障會隨著內核長度增加而變大,所以導通電流不與內核長度成正比。 | zh_TW |
dc.description.abstract | The electrical characteristics of InAs-Si heterojunction GAA NW TFET are simulated using Sentaurus TCAD produced by Synopsys. Results show that InAs-Si heterojunction can enlarge the on-state current compared with Si homo-junction and GAA structure can improve the subthreshold slope compared with single gate structure. The reasons are that the tunnel barrier width of InAs-Si heterojunction is smaller than Si homo-junction and the GAA structure has better gate control than single gate structure. Besides, the diameter of nanowire scarcely affects the performance of device due to the tunneling mainly occurring at nanowire surface. To further improve the subthreshold slope, we introduce Si pocket structure. This structure can further decrease the subthreshold slope by Si to Si tunneling mechanism. On the other hand, to further increase the on-state current, we introduce core shell structure. This structure can further increase on-state current because it enlarges the tunnel area. However, the on-state current does not increase proportional to the core length due to the tunnel barrier width in the direction across channel increases as the core length increasing. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T01:29:56Z (GMT). No. of bitstreams: 1 ntu-106-R04943068-1.pdf: 6994695 bytes, checksum: 8b42c6d272a6f80ee3d1cb5f843c8788 (MD5) Previous issue date: 2017 | en |
dc.description.tableofcontents | Content
中文摘要…………………………………………………………………………………I Abstract………………………………………………………………………………….II Content………………………………………………………………………………….III List of Figure…………………………………………………………………………...VI List of Table………………………………………………………………………....XXII Chapter 1 Introduction……………………………………………………………….......1 1.1 Background……………………………………………………………….…….....1 1.2 Band-to-band Tunneling……………………………...……………………….......3 1.3 Natural Length……………………………………………………………….……6 1.4 Motivation………………………………………………………………………...7 1.5 Thesis Organization……………………………………………………………….8 Chapter 2 Simulation Procedure and Convergence Test…………………………...........9 2.1 Sentaurus TCAD………………………….……………………………….............9 2.2 Sentaurus TCAD Workflow……………………………………………...………..9 2.3 Simulation Procedure…………………………...….……………………………12 2.4 Convergence Test……………………………………………………..................13 2.5 Simulation Divergence…………………………….……………………….........18 2.6 Symmetry of Result……………………………………………………………...20 2.7 Self-consistency………………………………………………………………….24 2.8 Time Consumption and Memory Usage…………………………………………24 2.9 Computer Specifications…………………………………………………………26 Chapter 3 InAs-Si Heterojunction GAA NW TFET…………………………..………..27 3.1 N-type InAs Nanowires on P-type Si Substrate…………………………............27 3.2 Fabrication of Device…………………………………………………................31 3.3 Device Structure and Simulation Parameters…………………………................32 3.4 Optimization…………………………………………………..............................34 3.5 Effect of NW Diameter…………………………………………………………..49 3.6 Effects of InAs-Si Heterojunction and GAA Structure………………………….54 Chapter 4 Si Pocket Structure……………………………………..………………........68 4.1 Device Structure and Simulation Parameters…………………………................68 4.2 Effect of Si Pocket Length…………………………………………………….....69 4.3 Results and Discussion……………………………………..................................72 Chapter 5 Core Shell Structure…………………………………………………………84 5.1 3D Simulation and 2D Simulation……………………………………..…….......84 5.2 Device Structure and Simulation Parameters…………………………...……….93 5.3 Effect of Core Diameter…………………………………………………….........96 5.4 Effect of Core Length…………………………………………………………..103 5.5 InAs Core Shell Structure………………………………………...……….........114 Chapter 6 Conclusion……………………………………………................................127 Bibliography………………………………..................................................................128 | |
dc.language.iso | en | |
dc.title | 以電腦輔助半導體工藝模擬及器件模擬工具設計砷化銦環繞式閘極奈米線穿隧式場效應電晶體之結構 | zh_TW |
dc.title | TCAD Design of InAs Gate-All-Around Nanowire Tunnel FET Structures | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 毛明華,王智祥,綦振瀛,鄭舜仁 | |
dc.subject.keyword | 穿隧式場效應電晶體,砷化銦-矽異質接面結構,環繞式閘極結構,矽袖珍結構,內核外殼結構,Sentaurus TCAD, | zh_TW |
dc.subject.keyword | TFET,InAs-Si heterojunction,GAA structure,Si pocket structure,core shell structure,Sentaurus TCAD, | en |
dc.relation.page | 131 | |
dc.identifier.doi | 10.6342/NTU201702594 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2017-08-04 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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