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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Liang-Hsin Chen | en |
dc.contributor.author | 陳良信 | zh_TW |
dc.date.accessioned | 2021-06-17T00:53:59Z | - |
dc.date.available | 2017-01-17 | |
dc.date.copyright | 2012-01-17 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-10-03 | |
dc.identifier.citation | [1] H.-H. Chang, J.-W. Lin, C.-Y. Yang, and S.-I. Liu, “A Wide-Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 40, no. 3, Mar. 2005.
[2] R.-J. Yang and S.-I. Liu, “A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm,” IEEE J. Solid-State Circuits, vol. 42, no. 2, Feb. 2007. [3] H. Chae, D. Shin, K. Kim, K.-W. Kim, Y.-J. Choi, C. Kim, “A Wide-Range All-Digital Multiphase DLL with Supply Noise Tolerance,” in IEEE Asian Solid-State Circuits Conference, pp. 421-424, Nov. 2008. [4] W.-J. Yun. et al., “A 0.1-to-1.5 GHz 4.2 mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66 nm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2008, pp. 282–283. [5] D. Shin, J. Song, H. Chae, and C. Kim, “A 7 ps Jitter 0.053 mm2 Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC,” IEEE J. Solid-State Circuits, vol. 44, no. 9, Sept. 2009. [6] J.-S. Wang, C.-Y. Cheng, J.-C. Liu, Y.-C. Liu, and Y.-M. Wang, “A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 45, no. 5, May. 2010. [7] A. Alvandpour, R. K. Krishnamurthy, D. Eckerbert, S. Apperson, B. Bloeche1, and S. Borkar, “A 3.5GHz 32mW 150nm Multiphase Clock Generator for High-Performance Microprocessors,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2003, pp. 112-113. [8] J.-S. Wang, Y.-M. Wang, C.-H. Chen, and Y.-C. Liu, “An Ultra Low Power, Fast Lock-In, Small Jitter, All-Digital Delay Locked Loop,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 422–423. [9] B. Mesgarzadeh and A. Alvandpour, “A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode,” IEEE J. Solid-State Circuits, vol. 44, no. 7, Sept. 2009. [10] S.-K. Kao, A.-J. Chen, and S.-I. Liu, “A 62.5–625-MHz Antireset All-Digital Delay-Locked Loop, ” IEEE Trans. Circuits Syst., vol. 54, no. 7, Jul. 2007. [11] B. W. Garlepp, et al., “A Portable Digital DLL for High-Speed CMOS Interface Circuits,” IEEE J. Solid-State Circuits, vol. 34, no 5, pp. 632-644, May 1999. [12] H.-H. Chang, C.-H. Sun, S.-I. Liu, “A Low-Jitter and Precise Multiphase Delay-Locked Loop Using Shifted Averaging VCDL,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2003, pp. 434-435. [13] H. Sutoh, K. Yamakoshi, and M. Ino, “Circuit Technique for Skew-Free Clock Distribution,” in IEEE Custom Integrated Circuits Conf., 1995, pp. 163–166. [14] Y. J. Jeon, et al., “A 66-333MHz 12mW Register-Controlled DLL with a Single Delay Line and Adaptive Duty-Cycle Clock Dividers for Production DDR SDRAMs,” IEEE J. Solid-State Circuits, vol. 39, no. 39, pp.2087-2092, Nov. 2004. [15] G. K. Dehng, et al., “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp.1128-1136, Aug. 2000. [16] D. Shin, J. Song, H. Chae, K.-W. Kim, Y.-J. Choi, and C. Kim, “A 7 ps Jitter 0.053 mm2 Fast Lock All-Digital DLL with Wide Range and High Resolution DCC,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 184-185. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66729 | - |
dc.description.abstract | 在IC設計領域當中,系統層級的整合已經成為現今的主要趨勢。延遲鎖定迴路被廣泛地使用在SoC(System-on-a-Chip)中,用來解決時脈歪斜問題和同步SoC中的每一個知識產權(Intellectual Property)和組件電路。然而,可作為一個IP的類比寬頻延遲鎖定迴路越來越難實現,而且也更難設計於高階製程當中。相較之下,全數位延遲鎖定迴路更容易實現於高階製程中,也易與數位系統整合。這份研究目的即在系統層級中,提出一個可視為IP的寬頻且快速鎖定的全數位延遲鎖定迴路。
此篇論文提出了一個創新電路─相位追蹤延遲器。使用相位追蹤延遲器的目的為取代一般使用在寬頻延遲鎖定迴路中的延遲線,並且將工作頻率範圍拓寬至6.7MHz-1.24GHz。除此之外,使用相位追蹤延遲器和以時脈同步延遲為基礎的控制單元使快速鎖定時間只需5個週期即可達成。有限狀態機和時間至數位轉換器為基礎的控制訊號產生器提供低抖動性能,而操作頻率在1.24GHz時,峰對峰抖動量測結果只有2.22ps。此晶片是使用台積電90nm CMOS製成,其核心電路面積為0.0318平方毫米。 | zh_TW |
dc.description.abstract | Nowadays, system-level integration has become the main trend in the IC design fields. DLLs are widely used in SoCs for solving the clock skew issues and synchronizing each intellectual property (IP) and module. However, wide-range analog DLLs which could be designed as an IP are becoming harder to be implemented and more difficult to be designed in the advanced processes nowadays. In contrast, the all-digital DLLs (ADDLLs) are easier to be realized and integrated with the digital systems in these advanced processes. A wide-range and fast-locking ADDLL as an IP for the system-level is proposed in this work.
In this thesis, a novel phase-tracing delay unit (PTDU) will be proposed as well. The purpose of using a PTDU is to replace with the long delay line which is used in wide-range DLLs and to enlarge the operating frequency range which is over 6.7MHz-1.24GHz. Moreover, the PTDU and the CSD-based control unit achieve fast-locking time which is only 5 cycles. The FSMs and TDC-based code generators provide low jitter performance, which is 2.22ps at 1.24GHz in our measurement. The chip was fabricated in TSMC 90nm CMOS process and occupied 0.0318mm2 active area. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T00:53:59Z (GMT). No. of bitstreams: 1 ntu-100-R98943126-1.pdf: 3223309 bytes, checksum: 0a32383fc54497728bc4634c70c38246 (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | List of Figures v
List of Tables ix Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivations 3 1.3 Thesis Organization 4 Chapter 2 An Overview of Delay-Locked Loops 5 2.1 Basic Concepts of the Delay-Locked Loops 5 2.2 Classification of Delay-Locked Loops 6 2.3 Analog Delay-Locked Loops 8 2.3.1 Phase Detector (PD) 9 2.3.2 Charge Pump (CP) and Loop Filter 11 2.3.3 Voltage-Controlled Delay Line (VCDL) 12 2.3.4 Stability Analysis 13 2.4 Digital Delay-Lock loops 14 2.4.1 Register-Controlled DLL 15 2.4.2 Counter-Controlled DLL 17 2.4.3 Successive Approximation Register-controlled DLL 18 2.5 Comparison of Analog DLL and Digital DLL 19 Chapter 3 A Wide-Range and Fast-Locking All-Digital Delay-Locked Loop Using a Phase-Tracing Delay Unit 21 3.1 Introduction 21 3.2 System Architecture 22 3.3 Phase-Tracing Delay Unit (PTDU) 23 3.3.1 Cyclic Pulse Generator (CPG) 27 3.3.2 Path Selector (PS) 28 3.3.3 FSM 29 3.3.3.1 Startup Circuit 31 3.3.4 Timing Controller (TC) 32 3.3.4.1 Frequency Detection 35 3.3.5 Complete Blocks for Low Frequencies 36 3.3.6 Simulation Results of the PTDU 37 3.4 Digital Phase Selector and Digital Phase Mixer (DPS and DPM) 40 3.5 Control Unit 44 3.5.1 Digital Phase Selector Control Code Generator (DPSCCG) 45 3.5.2 Phase Detector (PD) 47 3.5.3 Tuned Delay Unit 48 3.5.4 Digital Phase Mixer Control Code Generator (DSMCCG) 50 3.6 Edge Combiner 52 3.7 Locking Procedure 53 3.7.1 Simulation Results of the Locking Time 56 CHAPTER 4 Experimental Results 59 4.1 The test setup 59 4.2 The Measured Locking Time 62 4.3 The Measured Operating Frequency Range and Jitter 63 4.4 Summary 67 Chapter 5 Conclusion and Future Works 69 5.1 Conclusion 69 5.2 Future Works 70 Bibliography 71 | |
dc.language.iso | en | |
dc.title | 使用相位追蹤延遲器之寬頻且快速鎖定全數位延遲鎖定迴路 | zh_TW |
dc.title | A Wide-Range and Fast-Locking All-Digital Delay-Locked Loop Using a Phase-Tracing Delay Unit | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),李泰成(Tai-Cheng Lee) | |
dc.subject.keyword | 全數位延遲鎖定迴路,寬頻,快速鎖定,時脈同步延遲,時間至數位轉換器, | zh_TW |
dc.subject.keyword | All-Digital Delay-Locked Loop (ADDLL),Wide-Range,Fast-Locking,Clock-Synchronized Delay (CSD),Time-to-Digital Converter (TDC), | en |
dc.relation.page | 73 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2011-10-05 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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